ST STM32G4 Series Reference Manual page 1887

Advanced arm-based 32-bit mcus
Hide thumbs Also See for STM32G4 Series:
Table of Contents

Advertisement

RM0440
When the independent watchdog is started by writing the value 0x0000 CCCC in the
key register
When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the
IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
Once running, the IWDG cannot be stopped.
41.3.2
Window option
The IWDG can also work as a window watchdog by setting the appropriate window in the
IWDG window register
If the reload operation is performed while the counter is greater than the value stored in the
IWDG window register
The default value of the
updated, the window option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset
the downcounter to the
number calculation to generate the next reload.
Configuring the IWDG when the window option is enabled
1.
Enable the IWDG by writing 0x0000 CCCC in the
2.
Enable register access by writing 0x0000 5555 in the
3.
Write the IWDG prescaler by programming
0 to 7.
4.
Write the
5.
Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6.
Write to the
counter value in the
Note:
Writing the window value allows to refresh the Counter value by the RLR when
register (IWDG_SR)
Configuring the IWDG when the window option is disabled
When the window option it is not used, the IWDG can be configured as follows:
1.
Enable the IWDG by writing 0x0000 CCCC in the
2.
Enable register access by writing 0x0000 5555 in the
3.
Write the prescaler by programming the
7.
4.
Write the
5.
Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6.
Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA).
(IWDG_KR), the counter starts counting down from the reset value of 0xFFF.
(IWDG_WINR).
(IWDG_WINR), then a reset is provided.
IWDG window register (IWDG_WINR)
IWDG reload register (IWDG_RLR)
IWDG reload register
IWDG window register
IWDG reload register
is set to 0x0000 0000.
IWDG reload register
RM0440 Rev 1
IWDG key register
IWDG key register
IWDG prescaler register (IWDG_PR)
(IWDG_RLR).
(IWDG_WINR). This automatically refreshes the
(IWDG_RLR).
IWDG key register
IWDG prescaler register (IWDG_PR)
(IWDG_RLR).
Independent watchdog (IWDG)
(IWDG_KR), the
is 0x0000 0FFF, so if it is not
value and ease the cycle
(IWDG_KR).
IWDG key register
(IWDG_KR).
IWDG status
(IWDG_KR).
IWDG key register
(IWDG_KR).
IWDG
from
from 0 to
1887/2083
1894

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32G4 Series and is the answer not in the manual?

Table of Contents

Save PDF