Figure 52. Counter Timing Diagram, Internal Clock Divided By 4; Figure 53. Counter Timing Diagram, Internal Clock Divided By N; Figure 54. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded) - ST STM32F102 Series Reference Manual

Advanced-control timers (TIM1&TIM8)

Figure 52. Counter timing diagram, internal clock divided by 4

Figure 53. Counter timing diagram, internal clock divided by N

Figure 54. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
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CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
preloaded)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
0035
0036
1F 20
31 32 33 34 35 36 00 01 02 03 04 05 06 07
FF
RM0008
0000 0001
00
36