ST STM32G4 Series Reference Manual page 1823

RM0440
•
When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is
x t
I2CCLK
T
SDADEL
The total SDA output delay is:
t + {[SDADEL x (PRESC+1) + 1] x t
SYNC1
duration depends on these parameters:
t
SYNC1
–
–
–
–
In order to bridge the undefined region of the SCL falling edge, the user must program
SDADEL in such a way that:
{t +t
f (max)
SDADEL ≤ {t
Note: t / t
AF(min)
device datasheet for t
The maximum t
and Fast-mode Plus, but must be less than the maximum of t
This maximum must only be met if the device does not stretch the LOW period (t
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before
it releases the clock.
The SDA rising edge is usually the worst case, so in this case the previous equation
becomes:
SDADEL ≤ {t
Note: This condition can be violated when NOSTRETCH=0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to
t standard values.
VD;DAT
•
After t
clock because the data was not yet written in I2C_TXDR register, SCL line is kept at
low level during the setup time. This setup time is
t
PRESC
t
SCLDEL
In order to bridge the undefined region of the SDA transition (rising edge usually worst
case), the user must program SCLDEL in such a way that:
{[t + t
r (max)
Refer to
standard values.
The SDA and SCL transition time values to be used are the ones in the application. Using
the maximum values from the standard increases the constraints for the SDADEL and
SCLDEL calculation, but ensures the feature whatever the application.
.
impacts the hold time
SCL falling slope
When enabled, input delay brought by the analog filter: t
When enabled, input delay brought by the digital filter: t
Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)
-t - [(DNF +3) x t
HD;DAT (min)
AF(min)
-t
HD;DAT (max)
AF(max)
are part of the equation only when the analog filter is enabled. Refer to
AF(max)
values.
AF
can be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode
HD;DAT
-t
VD;DAT (max) r (max)
Table 371: I2C-SMBUS specification data setup and hold times
delay, or after sending SDA output in case the slave had to stretch the
SDADEL
= (PRESC+1) x t
I2CCLK.
impacts the setup time
] / [
(PRESC+1)] x t
SU;DAT (min)
Table 371: I2C-SMBUS specification data setup and hold times
Inter-integrated circuit (I2C) interface
t = SDADEL x t
SDADEL PRESC
t
HD;DAT.
}
I2CCLK
]} / {(PRESC +1) x t
I2CCLK
- [(DNF+4) x t
I2CCLK
-260 ns - [(DNF+4) x t
t
SU;DAT .
]} - 1 <=
I2CCLK
RM0440 Rev 1
where
+ t t
I2CCLK PRESC
< t
AF(min) AF
= DNF
DNF
I2CCLK
]} / {(PRESC +1) x t
I2CCLK
by a transition time.
VD;DAT
]} / {(PRESC +1) x t
I2CCLK
for t
t = (SCLDEL+1) x t
SCLDEL
SCLDEL
for t
= (PRESC+1)
< t
AF(max)
t
x
I2CCLK
} ≤ SDADEL
}
) of the
LOW
}.
I2CCLK
, t , t and
f r HD;DAT
where
PRESC
and t
r SU;DAT
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