Figure 135. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded); Figure 136. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded) - ST STM32WL55JC Reference Manual

Advanced-control timer (TIM1)
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
732/1454
Figure 137. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
05
(UIF)
Figure 138. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
0002
(UIF)
RM0453 Rev 2
04
03 02 01 00 36
0001 0000
35 34 33 32
31
0036 0034
0035
RM0453
30 2F
MS31184V1
0033
MS31185V1