Figure 47. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded); Figure 48. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded) - ST STM32F100 Series Reference Manual

Advanced arm-based 32-bit mcus

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Figure 47. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

Timerclock = CK_CNT

Update event (UEV)

Update interrupt flag (UIF)

Auto-reload preload register

Figure 48. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

Auto-reload preload

Auto-reload shadow

Write a new value in TIMx_ARR

Counter register

Counter overflow

Write a new value in TIMx_ARR

RM0041 Rev 6

Advanced-control timer (TIM1)

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