ST STM32G4 Series Reference Manual page 1810

Serial audio interface (SAI)
Bits 31:0 DATA[31:0]: Data
A write to this register loads the FIFO provided the FIFO is not full.
A read from this register empties the FIFO if the FIFO is not empty.
39.5.16 Data register (SAI_BDR)
Address offset: 0x040
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 DATA[31:0]: Data
A write to this register loads the FIFO provided the FIFO is not full.
A read from this register empties the FIFO if the FIFO is not empty.
39.5.17 PDM control register (SAI_PDMCR)
Address offset: 0x0044
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 CKEN4: Clock enable of bitstream clock number 4
This bit is set and cleared by software.
0: SAI_CK4 clock disabled
1: SAI_CK4 clock enabled
Note: It is not recommended to configure this bit when PDMEN = 1.
Bit 10 CKEN3: Clock enable of bitstream clock number 3
This bit is set and cleared by software.
0: SAI_CK3 clock disabled
1: SAI_CK3 clock enabled
Note: It is not recommended to configure this bit when PDMEN = 1.
1810/2083
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
CKEN4 CKEN3 CKEN2 CKEN1
rw rw rw
24 23 22 21
DATA[31:16]
rw rw rw rw
8 7 6 5
DATA[15:0]
rw rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res.
rw
RM0440 Rev 1
20 19 18
rw rw rw
4 3 2
rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
MICNBR[1:0] Res. Res.
rw rw
RM0440
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
Res. PDMEN
rw