Figure 131. Counter Timing Diagram, Internal Clock Divided By N; Figure 132. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded) - ST STM32F412 Reference Manual

RM0402 General-purpose timers (TIM2 to TIM5)

Figure 131. Counter timing diagram, internal clock divided by N

CK_INT
Timerclock = CK_CNT
Counter register
1F 20 00
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
MSv37302V1
Figure 132. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register FF 36
Write a new value in TIMx_ARR
MSv37303V1
RM0402 Rev 6 489/1163
544