Motorola PowerQUICC II MPC8280 Series Reference Manual page 104

Architecture Overview
• Memory controller supporting 12 memory banks that can be allocated for either the
system or the local bus. The memory controller is an enhanced version of the
MPC860 memory controller. It supports three user-programmable machines.
Besides all MPC860 features, the memory controller also supports SDRAM with
page mode and address data pipeline.
• Supports JTAG controller IEEE 1149.1 test access port (TAP).
• A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt
timer, and other system functions useful in embedded applications.
• Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM
(MCM69C232/MCM69C432).
1.2.3 Communications Processor Module (CPM)
The CPM contains features that allow the MPC8280 to excel in a variety of applications
targeted mainly for networking and telecommunication markets.
The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP
performance and additional hardware and microcode routines that support high bit rate
protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps
full-duplex).
The following list summarizes the major features of the CPM:
• The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM
local bus) from the 60x bus (used by the system core). With this separate bus, the CP
does not affect the performance of the G2_LE core. The CP handles the lower layer
tasks and DMA control activities, leaving the G2_LE core free to handle higher
layer activities. The CP has an instruction set optimized for communications, but can
also be used for general-purpose applications, relieving the system core of small
often repeated tasks.
• Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst
transfers to the 60x bus and to the local bus.
• Three full-duplex, serial fast communications controllers (FCCs) supporting ATM
(155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces
on the MPC8280), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates
(45 Mbps) and totally transparent operation. Each FCC can be configured to
transmit fully transparent and receive HDLC or vice-versa. (Note that the MPC8270
does not support ATM (155 Mbps) protocol.)
• Two multichannel controllers (MCCs) that can handle an aggregate of 256 X 64
Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces.
The MCC also supports super-channels of rates higher than 64 Kbps and
subchanneling of the 64-Kbps channels.
1-8
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
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