Architecture Overview - Motorola PowerQUICC II MPC8280 Series Reference Manual

Architecture Overview

1.2 Architecture Overview
The MPC8280 has two external buses to accommodate bandwidth requirements from the
high-speed system core and the very fast communications channels. Figure 1-1 shows the
block diagram of the superset MPC8280 device. Features that are device- or
package-specific are noted. For package information, refer to the MPC8280
PowerQUICC II Family Hardware Specifications (order number: MPC8280EC).
G2_LE Core
Communication Processor Module (CPM)
Timers
Interrupt
Controller
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
Baud Rate
Generators
1
MCC1 MCC2 FCC1 FCC2
TC Layer Hardware
8 TDM Ports
Notes:
1
MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)
2
MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have
only 1 SI block and 4 TDM ports (TDM2[A–D]).
3
MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)
Both the system core and the CPM have an internal PLL, which allows independent
optimization of the frequencies at which they run. The system core and CPM are both
connected to the 60x bus.
1-6
Freescale Semiconductor, Inc.
16 Kbytes
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
32 KB 32 KB
Instruction Data
RAM
RAM
1
IMA
Microcode
FCC3 SCC1 SCC2 SCC3
1
Time Slot Assigner
Serial Interface
2
3 MII or RMII
Ports
Figure 1-1. MPC8280 Block Diagram
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
System Interface Unit
(SIU)
Bus Interface Unit
60x-to-PCI
Bridge
60x-to-Local
Bridge
Memory Controller
Serial
DMAs
Clock Counter
4 Virtual
System Functions
IDMAs
SCC4/ SMC1 SMC2 SPI
USB
2
Non-Multiplexed
2 UTOPIA
I/O
3
Ports
60x Bus
PCI Bus
32 bits, up to 66 MHz
or
Local Bus
32 bits, up to 100 MHz
2
I C
MOTOROLA