Motorola PowerQUICC II MPC8280 Series Reference Manual page 100

Features
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O
transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media
independent interface (MII) or reduced media independent interface (RMII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface,
AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types,
up to 64 K external connections (no ATM support for the MPC8270)
– Transparent
– HDLC—Up to T3 rates (clear channel)
– FCC2 can also be connected to the TC layer (MPC8280 only)
— Two multichannel controllers (MCCs) (one MCC on the MPC8270)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each
MCC can be split into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or
multiple TDM interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the
MPC860, supporting the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Universal serial bus (USB) controller
– USB 2.0 full/low rate compatible
– USB host mode
–Supports control, bulk, interrupt, and isochronous data transfers
–CRC16 generation and checking
–NRZI encoding/decoding with bit stuffing
–Supports both 12- and 1.5-Mbps data rates (automatic generation of
preamble token and data rate configuration). Note that low-speed operation
requires an external hub.
–Flexible data buffers with multiple buffers per frame
1-4
Freescale Semiconductor, Inc.
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
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