Motorola PowerQUICC II MPC8280 Series Reference Manual page 108

MPC8280 Configurations
any given implementation: The CPM architecture has the advantage of using common
hardware resources for many different protocols, and applications. Two physical factors
limit the functionality in any given system—pinout and performance.
1.6.1 Pin Configurations
Some pins have multiple functions. Choosing one function may preclude the use of another.
Information about multiplexing constraints can be found in Chapter 16, "CPM
Multiplexing," and Chapter 41, "Parallel I/O Ports."
1.6.2 Serial Performance
Serial performance depends on a number of factors:
• Serial rate versus CPM clock frequency for adequate sampling on serial channels
• Serial rate and protocol versus CPM clock frequency for CP protocol handling
• Serial rate and protocol versus bus bandwidth
• Serial rate and protocol versus system core clock for adequate protocol handling
The second item above is addressed in this section—the CP's ability to handle high bit-rate
protocols in parallel. Slow bit-rate protocols do not significantly affect those numbers.
Table 1-2 describes a few options to configure the fast communications channels on the
MPC8280. The frequency specified is the minimum CPM frequency necessary to run the
mentioned protocols concurrently at full-duplex.
FCC1 FCC2
155-Mbps ATM 100 BaseT
100 BaseT 100 BaseT
155-Mbps ATM
100 BaseT 100 BaseT
155-Mbps ATM
100 BaseT
45-Mbps HDLC
45-Mbps HDLC 100 BaseT
100 BaseT
1
For the MPC8270 see Table 1-3.
1-12
Freescale Semiconductor, Inc.
Table 1-2. Serial Performance
FCC3
100 BaseT
100 BaseT
128 * 64 Kbps channels
128 * 64 Kbps channels
256 * 64 Kbps channels
256 * 64 Kbps channels
256 * 64 Kbps
256 * 64 Kbps
16 * 576 Kbps
MPC8280 PowerQUICC II Family Reference Manual
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1
CPM Clock
MCC
(MHz)
133
133
133
133
166
133
133
166
166
60x Bus Clock
(MHz)
66
66
66
66
66
66
66
66
66
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