Motorola PowerQUICC II MPC8280 Series Reference Manual page 132

Programming Model
2.3.1.2 MPC8280-Specific Registers
The set of registers specific to the MPC603e are also shown in Figure 2-2. Most of these
are described in the G2 Core Reference Manual and are implemented in the MPC8280 as
follows:
• MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS,
ICMP, and RPA. These registers facilitate the software required to search the page
tables in memory.
• IABR and IABR2. These registers facilitate the setting of instruction address
breakpoints.
• DABR and DABR2. These registers facilitate the setting of data address
breakpoints.
• IBCR and DBCR. These registers give further control to the instruction and data
address breakpoints.
The hardware implementation-dependent registers (HIDx) are implemented differently in
the MPC8280, and they are described in the following subsections.
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)
Figure 2-3 shows the MPC8280 implementation of HID0.
0 1 2
EMCP — EBA EBD
16 17 18 19
ICE DCE ILOCK DLOCK ICFI DCFI
Figure 2-3. Hardware Implementation Register 0 (HID0)
Table 2-1 shows the bit definitions for HID0.
Bits Name
0 EMCP Enable machine check input pin
0 The assertion of the MCP does not cause a machine check exception.
1 Enables the entry into a machine check exception based on assertion of the MCP input,
detection of a cache parity error, detection of an address parity error, or detection of a data
parity error.
Note that the machine check exception is further affected by MSR[ME], which specifies whether
the processor checkstops or continues processing.
1 — Reserved
2-12
Freescale Semiconductor, Inc.
3 4 6 7
— PAR DOZE
20 21 22 23
—
Table 2-1. HID0 Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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8 9 10 11
— STOP DPM
24 25 26 27
IFEM — FBIOB ABE
Description
12 14 15
— NHR
28 29 30 31
— NOOPTI
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