Motorola PowerQUICC II MPC8280 Series Reference Manual page 126

G2_LE Core Features
Instructions issued beyond a predicted branch do not complete execution until the branch
is resolved, preserving the programming model of sequential execution. If any of these
instructions are to be executed in the BPU, they are decoded but not issued. Instructions to
be executed by the IU, LSU, and SRU are issued and allowed to complete up to the register
write-back stage. Write-back is allowed when a correctly predicted branch is resolved, and
instruction execution continues without interruption on the predicted path. If branch
prediction is incorrect, the instruction unit flushes all predicted path instructions, and
instructions are issued from the correct path.
2.2.2 Instruction Queue and Dispatch Unit
The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and
loads up to two instructions from the instruction unit during a single cycle. The instruction
fetch unit continuously loads as many instructions as space in the IQ allows. Instructions
are dispatched to their respective execution units from the dispatch unit at a maximum rate
of two instructions per cycle. Reservation stations at the IU, LSU, and SRU facilitate
instruction dispatch to those units. The dispatch unit checks for source and destination
register dependencies, determines dispatch serializations, and inhibits subsequent
instruction dispatching as required. Section 2.7, "Instruction Timing," describes instruction
dispatch in detail.
2.2.3 Branch Processing Unit (BPU)
The BPU receives branch instructions from the fetch unit and performs CR lookahead
operations on conditional branches to resolve them early, achieving the effect of a
zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when an unresolved conditional branch instruction is encountered,
instructions are fetched from the predicted target stream until the conditional branch is
resolved.
The BPU contains an adder to compute branch target addresses and three user-control
registers—the link register (LR), the count register (CTR), and the CR. The BPU calculates
the return pointer for subroutine calls and saves it into the LR for certain types of branch
instructions. The LR also contains the branch target address for the Branch Conditional to
Link Register (bclrx) instruction. The CTR contains the branch target address for the
Branch Conditional to Count Register (bcctrx) instruction. The contents of the LR and
CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather
than GPRs or FPRs, execution of branch instructions is largely independent from execution
of other instructions.
2-6
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