Motorola PowerQUICC II MPC8280 Series Reference Manual page 135

Table 2-1. HID0 Field Descriptions (continued)
Bits Name
25–26 — Reserved
27 FBIOB • Force branch indirect on bus.
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally.
28 ABE Address broadcast enable
0 dcbf, dcbi, and dcbst instructions are not broadcast on the 60x bus.
1 dcbf, dcbi, and dcbst generate address-only broadcast operations on the 60x bus.
29–30 — Reserved
31 NOOPTI No-op the data cache touch instructions.
0 The dcbt and dcbtst instructions are enabled.
1 The dcbt and dcbtst instructions are no-oped globally.
1
See Chapter 10, "Power Management," of the G2 Core Reference Manual for more information.
2
See Chapter 4, "Instruction and Data Cache Operation," of the G2 Core Reference Manual for more information.
2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)
The MPC8280 implementation of HID1 is shown in Figure 2-4.
0 4 5
PLLCFG
Figure 2-4. Hardware Implementation-Dependent Register 1 (HID1)
Table 2-2 shows the bit definitions for HID1.
Bits Name
0–4 PLLCFG PLL configuration setting. These bits reflect the state of the PLL_CFG[0:4] signals.
5–31 — Reserved
2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)
The processor core implements an additional hardware implementation-dependent register,
shown in Figure 2-5.
0
—
Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)
MOTOROLA
Freescale Semiconductor, Inc.
Table 2-2. HID1 Field Descriptions
12 13 14 15
HBE — SFP
Chapter 2. G2_LE Core
For More Information On This Product,
Go to: www.freescale.com
Description
—
Function
16 18 19 23 24
IWLCK —
Programming Model
31
26 27 31
DWLCK —
2-15