Motorola PowerQUICC II MPC8280 Series Reference Manual page 106

Differences between MPC860 and MPC8280
VCCSYN/GNDSYN/VCCSYN1//VDDH/
SMI/PCI_FRAME/L_A15
CKSTOP_OUT/PCI_IRDY/L_A17
PCI_DEVSEL/L_A19
CPCI_HS_ES/PCI_REQ1/L_A24
CPCI_HS_LED/PCI_GNT1/L_A26 <⎯⎯⎯
CPCI_HS_ENUM/PCI_CLK/L_A27
CORE_SRESET/PCI_RST/L_A28
PCI_AD[0–31]/LCL_D[0–31]
PCI_C/BE[0–3]/LCL_DP[0–3]
PCI_CFG[3–0]/LBS[0–3]/
LSDDQM[0–3]/LWE[0–3]
PCI_MODCK_H0/LGPL0/LSDA10 <⎯⎯⎯
PCI_MODCK_H1/LGPL1/LSDWE <⎯⎯⎯
PCI_MODCK_H2/LGPL2/LSDRAS/LOE <⎯⎯⎯
PCI_MODCK_H3/LGPL3/LSDCAS <⎯⎯⎯
LPBS/LGPL4/LUPMWAIT/LGTA
PCI_MODCK/LGPL5
PCI_RST/PORESET⎯⎯⎯> 1
BNKSEL[0]/TC[0]/AP[1]/MODCK1<⎯⎯>
BNKSEL[1]/TC[1]/AP[2]/MODCK2<⎯⎯>
BNKSEL[2]/TC[2]/AP[3]/MODCK3<⎯⎯>
1.4 Differences between MPC860 and MPC8280
The following MPC860 features are not included in the MPC8280.
• On-chip crystal oscillators (must use external oscillator)
• 4-MHz oscillator (input clock must be at the bus speed)
• Low power (stand-by) modes
1-10
Freescale Semiconductor, Inc.
VDD/VSS ⎯⎯⎯> 100
<⎯⎯> 1
PCI_PAR/L_A14
<⎯⎯> 1
<⎯⎯> 1
PCI_TRDY/L_A16
<⎯⎯> 1
<⎯⎯> 1
PCI_STOP/L_A18
<⎯⎯> 1
<⎯⎯> 1
PCI_IDSEL/L_A20
<⎯⎯> 1
PCI_PERR/L_A21
<⎯⎯> 1
PCI_SERR/L_A22
<⎯⎯> 1
PCI_REQ0/L_A23
<⎯⎯> 1
<⎯⎯> 1
PCI_GNT0/L_A25
1
<⎯⎯> 1
<⎯⎯> 1
<⎯⎯> 1
PCI_INTA/L_A29
<⎯⎯> 1
PCI_REQ2/L_A30
<⎯⎯> 1
DLLOUT/L_A31
<⎯⎯> 32
<⎯⎯> 4
<⎯⎯⎯
4
1
1
1
1
<⎯⎯> 1
<⎯⎯> 1
<⎯⎯> 1
LWR
<⎯⎯> 32
PA[0–31]
<⎯⎯> 28
PB[4–31]
<⎯⎯> 32
PC[0–31]
<⎯⎯> 28
PD[4–31]
RSTCONF⎯⎯⎯> 1
HRESET<⎯⎯> 1
SRESET<⎯⎯> 1
QREQ<⎯⎯⎯ 1
XFC⎯⎯⎯> 1
CLKIN1⎯⎯⎯> 1
TRIS⎯⎯⎯> 1
1
1
1
PCI_MODE ⎯⎯⎯> 1
CLKIN2 ⎯⎯⎯> 1
NC ⎯⎯⎯> 2
Figure 1-2. MPC8280 External Signals
MPC8280 PowerQUICC II Family Reference Manual
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32 <⎯⎯>
A[0–31]
5 <⎯⎯>
TT[0–4]
4 <⎯⎯>
TSIZ[0–3]
1 <⎯⎯>
TBST
1 <⎯⎯>
GBL/IRQ1
1 <⎯⎯>
CI/BADDR29/IRQ2
L
1 <⎯⎯>
WT/BADDR30/IRQ3
O
1 <⎯⎯⎯ L2_HIT/IRQ4
1 <⎯⎯>
C
CPU_BG/BADDR31/IRQ5/CINT
1 ⎯⎯⎯> CPU_DBG
A
1 ⎯⎯⎯> CPU_BR
L
1 <⎯⎯>
BR
1 <⎯⎯>
6
BG
1 <⎯⎯>
B
ABB/IRQ2
0
1 <⎯⎯>
TS
U
x
1 <⎯⎯>
AACK
S
1 <⎯⎯>
ARTRY
1 <⎯⎯>
B
DBG
1 <⎯⎯>
DBB/IRQ3
U
64 <⎯⎯>
D[0–63]
S
1 <⎯⎯>
NC/DP0/RSRV/EXT_BR2
1 <⎯⎯>
IRQ1/DP1/EXT_BG2
1 <⎯⎯>
IRQ2/DP2/TLBISYNC/EXT_DBG2
1 <⎯⎯>
IRQ3/DP3/CKSTP_OUT/EXT_BR3
M
1 <⎯⎯>
IRQ4/DP4/CORE_SRESET/EXT_BG3
E 1 <⎯⎯>
IRQ5/DP5/TBEN/EXT_DBG3/CINT
1 <⎯⎯>
M IRQ6/DP6/CSE0
1 <⎯⎯>
IRQ7/DP7/CSE1
C
1 <⎯⎯>
PSDVAL
1 <⎯⎯>
TA
1 <⎯⎯>
TEA
1 <⎯⎯>
IRQ0/NMI_OUT
1 <⎯⎯>
IRQ7/INT_OUT/APE
P
10 ⎯⎯⎯> CS[0–9]
I
1 <⎯⎯>
CS[10]/BCTL1
O
1 <⎯⎯>
CS[11]/AP[0]
2 ⎯⎯⎯> BADDR[27–28]
1 ⎯⎯⎯> ALE
M
1 ⎯⎯⎯> BCTL0
E
8 ⎯⎯⎯> PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
M
R
1 ⎯⎯⎯> PSDA10/PGPL0
C
1 ⎯⎯⎯> PSDWE/PGPL1
S
1 ⎯⎯⎯> POE/PSDRAS/PGPL2
T
1 ⎯⎯⎯> PSDCAS/PGPL3
1 <⎯⎯>
PGTA/PUPMWAIT/PGPL4/PPBS
C
1 ⎯⎯⎯> PSDAMUX/PGPL5
1 <⎯⎯⎯ TMS
L
J
1 <⎯⎯⎯ TDI
K
T
1 <⎯⎯⎯ TCK
A
1 <⎯⎯⎯ TRST
G
1 ⎯⎯⎯> TDO
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