ST STM32L4+ Series Reference Manual page 1692

Inter-integrated circuit (I2C) interface
Example SMBus slave receiver 2 bytes + PEC
NBYTES
EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd PEC
Example SMBus slave receiver 2 bytes + PEC, with ACK control
(RELOAD=1/0)
S Address
NBYTES
EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 1, PECBYTE=1, RELOAD=1, set ADDRCF
EV2: RXNE-TCR ISR: rd data1, program NACK=0 and NBYTES = 1
EV3: RXNE-TCR ISR: rd data2, program NACK=0, NBYTES = 1 and RELOAD=0
EV4: RXNE-TCR ISR: rd PEC
This section is relevant only when SMBus feature is supported. Refer to
implementation.
In addition to I2C master transfer management (refer to
some additional software flowcharts are provided to support SMBus.
SMBus Master transmitter
When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts is NBYTES-1. So if the PECBYTE bit is
set when NBYTES=0x1, the content of the I2C_PECR register is automatically transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
must be selected (AUTOEND=1). In this case, the STOP condition automatically follows the
PEC transmission.
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Figure 486. Bus transfer diagrams for SMBus slave receiver (SBC=1)
ADDR
S Address A data1
EV1
ADDR RXNE,TCR
A data1
E V 1
1
RXNE RXNE
A data2 A PEC
EV2 EV3
3
RXNE,TCR
A data2 A
E V 2 E V 3
RM0432 Rev 6
RXNE
A P
EV4
legend :
RXNE
PEC A P
EV4
Section 49.3: I2C
Section 49.4.9: I2C master
RM0432
legend:
transmission
reception
SCL stretch
transmission
reception
SCL stretch
MS19870V2
mode)