Dfsdm Filter X Extremes Detector Maximum Register; (Dfsdm_Fltxexmax); Dfsdm Filter X Extremes Detector Minimum Register; (Dfsdm_Fltxexmin) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Digital filter for sigma delta modulators (DFSDM)

Bits 11:8 CLRAWHTF[3:0]: Clear the analog watchdog high threshold flag

CLRAWHTF[y]=0: Writing '0' has no effect

CLRAWHTF[y]=1: Writing '1' to position y clears the corresponding AWHTF[y] bit in the

DFSDM_FLTxAWSR register

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 CLRAWLTF[3:0]: Clear the analog watchdog low threshold flag

CLRAWLTF[y]=0: Writing '0' has no effect

CLRAWLTF[y]=1: Writing '1' to position y clears the corresponding AWLTF[y] bit in the

DFSDM_FLTxAWSR register

DFSDM filter x extremes detector maximum register

Address offset: 0x130 + 0x80 * x, (x = 0 to 1)

Reset value: 0x8000 0000

Bits 31:8 EXMAX[23:0]: Extremes detector maximum value

These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx.

EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.

Bits 7:2 Reserved, must be kept at reset value.

Bits 1:0 EXMAXCH[1:0]: Extremes detector maximum data channel.

These bits contains information about the channel on which the data is stored into EXMAX[23:0].

Bits are cleared by reading of this register.

Address offset: 0x134 + 0x80 * x, (x = 0 to 1)

Reset value: 0x7FFF FF00

RM0402 Rev 6

EXMAXCH[1:0]

EXMINCH[1:0]

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