Dfsdm Filter X Analog Watchdog Clear Flag Register; (Dfsdm_Fltxawcfr); Dfsdm Filter X Extremes Detector Maximum Register; (Dfsdm_Fltxexmax) - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F423:

Table of Contents

Digital filter for sigma delta modulators (DFSDM)

DFSDM filter x analog watchdog clear flag register

Address offset: 0x12C + 0x80 * x, (x = 0 to 3)

Reset value: 0x0000 0000

CLRAWHTF[7:0]

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag

CLRAWHTF[y]=0: Writing '0' has no effect

CLRAWHTF[y]=1: Writing '1' to position y clears the corresponding AWHTF[y] bit in the

DFSDM_FLTxAWSR register

Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag

CLRAWLTF[y]=0: Writing '0' has no effect

CLRAWLTF[y]=1: Writing '1' to position y clears the corresponding AWLTF[y] bit in the

DFSDM_FLTxAWSR register

Address offset: 0x130 + 0x80 * x, (x = 0 to 3)

Reset value: 0x8000 0000

Bits 31:8 EXMAX[23:0]: Extremes detector maximum value

These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx.

EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 EXMAXCH[2:0]: Extremes detector maximum data channel.

These bits contains information about the channel on which the data is stored into EXMAX[23:0].

Bits are cleared by reading of this register.

RM0430 Rev 8

CLRAWLTF[7:0]

EXMAXCH[2:0]

Do you have a question about the STM32F423 and is the answer not in the manual?