Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 765

The Itanium architecture does not allow the outcome r1 = x and r2 = 0 in this
execution either. Unlike the execution in
between the values that M3 produces and the values that M4 consumes. However, there
is a RAW through register r1 from M3 to C1 and a RAW through register p1 from C1 to
M4. Thus, by transitivity,
The execution in
dependency.
Table 2-8.
st
st.rel
This execution is semantically the same as the execution in
execution uses a control dependency rather than predication to conditionally execute
M4. As a result, the outcome r1 = x and r2 = 0 is not allowed in the
execution.
The execution of the load M4 is data-dependent on the value of p2 that the branch B1
uses to resolve. Further, p2 is dependent on the value of r1 that the load M3 produces
through the compare C1. Thus,
The execution in
loads are truly independent.
Table 2-9.
st
st.rel
In this execution, there is no dependency between M3 and M4, and thus, there are no
constraints on the relative ordering of M3 and M4. Like the execution in
data-dependent on the value of p2 that the branch B1 uses to resolve. However, p2 is
independent of the value that the load M3 produces (specifically, because the compare
does not use the value of register r1 that the load produces). Thus, there is no chain of
dependencies between M3 and M4 and therefore there are no constraints on the
relative ordering of M3 and M4. As a result, all outcomes are allowed in this execution.
Volume 2, Part 2: MP Coherence and Synchronization
 .
M3 M4
Table 2-8 illustrates a similar construct but introduces a control
Memory Ordering and Data and Control Dependencies
Processor #0
[x] = 1 // M1
[y] = x // M2
Outcome: r1 = x and r2 = 0 is not allowed

M3
Table 2-9 is a variation on the execution from
Memory Ordering and Control Dependency
Processor #0
[x] = 1 // M1
[y] = x // M2
Outcome: all are allowed
Table 2-6, there is no direct dependency
ld r1 = [y];;
cmp.eq p1, p2 = r1, x // C1
(p2)br t
ld r2 = [x]
t:
Table
.
M4
ld r1 = [y]
cmp p1, p2 = r3, x // C1
(p2) br t
ld r2 = [x]
t:
Processor #1
// M3
// B1
// M4
2-7; however, this
Table 2-8
Table 2-8 where the
Processor #1
// M3
// B1
// M4
Table 2-8, M4 is
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