Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 305

Table 4-4.
TLB.ar
6
7
a. RSC.pl, for RSE fills and spills; PSR.cpl for all other accesses.
b. User execute only pages can be enforced by setting PL to 3.
Software can verify page level permissions by the probe (regular_form probe or
probe.fault) instruction, which checks accessibility to a given virtual page by verifying
privilege levels, page level read and write permission, and protection key read and
write permission.
Execute-only pages (TLB.ar 7) can be used to promote the privilege level on entry into
the operating system. User level code would typically branch into a promotion page
(controlled by the operating system) and execute the Enter Privileged Code (epc)
instruction. When epc successfully promotes, the next instruction group is executed at
the target privilege level specified by the promotion page. A procedure return branch
type (br.ret) can demote the current privilege level.
4.1.1.7 Page Sizes
A range of page sizes are supported to assist software in mapping system resources
and improve TLB/VHPT utilization. Typically, operating systems will select a small range
of fixed page sizes to implement virtual memory algorithms. Larger pages may be
statically allocated. For example, large areas of the virtual address space may be
reserved for operating system kernels, frame buffers, or memory-mapped I/O regions.
Software may also elect to pin these translations, by placing them in the translation
registers.
Table 4-5
models. Insertable page sizes can be specified in the translation cache, the translation
registers, the region registers and the VHPT. Insertable page sizes can also be used as
parameters to TLB purge instructions (ptc.l, ptc.g, ptc.ga or ptr). Page sizes that
are purgeable only may only be used as parameters to TLB purge instructions.
Processors may also support additional insertable and purgeable page sizes. Please see
the processor-specific documentation for further information on the page sizes
supported by the Itanium processor.
Volume 2, Part 1: Addressing and Protection
Page Access Rights (Continued)
Privilege Level
TLB.pl
3 2
3 RWX RW
2 – RWX
1 – –
0 – –
3 X X
2 XP2 X
1 XP1 XP1
0 XP0 XP0
lists insertable and purgeable page sizes that are supported by all processor
a
1 0
RW RW read, write, execute / read, write
RW RW
RWX RW
– RW
X RX exec, promote
X RX
X RX
XP0 RX
Description
b
/ read, execute
2:57