Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 544

11.3 Machine Checks
11.3.1 PALE_CHECK
When a machine check abort (MCA) occurs, PALE_CHECK is responsible for saving
minimal processor state to a uncacheable platform-specific memory location previously
registered with PAL via the PAL_MC_REGISTER_MEM procedure. This platform location
is called the Minimal State Save Area (min-state save area) and is described in
Section 11.3.2.4, "Processor Min-state Save Area Layout" on page
is also responsible for correcting processor related errors whenever possible.
PALE_CHECK terminates either by returning to the interrupted context or by branching
to SALE_ENTRY, passing the state of the processor at the time of the error. The level of
recovery provided by PALE_CHECK is implementation dependent and is beyond the
scope of this specification.
At the hand-off from PALE_CHECK to SALE_ENTRY, error information is passed in the
Processor State Parameter described in
(GR 18)" on page
is available by calling the PAL_MC_ERROR_INFO procedure. Information about
implementation-dependent state is available by calling the PAL_MC_DYNAMIC_STATE
procedure. The interrupted process may be resumed by calling the PAL_MC_RESUME
procedure. See Section 11.3.3, "Returning to the Interrupted Process" for more
information on returning to the interrupted context and
Procedures"
Code for handling machine checks must take into consideration the possibility that
nested machine checks may occur. A nested machine check is a machine check that
occurs while a previous machine check is being handled.
PALE_CHECK is entered in the following conditions:
• When PSR.mc = 0 and an error occurs which results in a machine check, or
• When PSR.mc changes from 1 to 0 and there is a pending machine check from an
earlier error.
PSR.mc is set to 1 by the hardware when PALE_CHECK is entered. When PALE_CHECK
branches to SALE_ENTRY, PSR.mc remains set (PSR.mc is restored to its original value
if PALE_CHECK terminates by returning to the interrupted context). SAL must not clear
PSR.mc to 0 before all the information from the current machine check is logged. If SAL
enables machine checks (by setting PSR.mc=0) during the SAL MCA handling, there is
a potential for the error logs in the processor and the min-state save area to be
overwritten by a subsequent MCA event.
The error information logged will reflect the state at the time the error occurred. State
information from a different point in time will NOT be logged. If complete information is
not available a code is logged which indicates that the information is not available.
• The processor state information used to resume a process for which an error has
been corrected will reflect the state at the time the machine check interruption
occurred and will be sufficient to resume the interrupted process.
• When a single error is signalled multiple times (for example, multiple operations to
a single bad cache line), hardware and firmware will be able to perform the same
logging and recovery as if the error had been signalled once.
2:296
2:299. After exit from PALE_CHECK, more detailed error information
on page 2:353 for detailed descriptions of all these procedure calls.
Section 11.3.2.1, "Processor State Parameter
Section 11.10, "PAL
Volume 2, Part 1: Processor Abstraction Layer
2:302. PALE_CHECK