Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 408

7.2.2 Performance Monitor Overflow Status Registers
(PMC[0]..PMC[3])
Performance monitor interrupts may be caused by an overflow from a generic
performance monitor or an implementation-dependent event from a model-specific
monitor. The four performance monitor overflow registers (PMC[0]...PMC[3]) shown in
Figure 7-6
Each of the 252 overflow bits in the performance monitoring overflow status
registers(PMC[0]...PMC[3]) corresponds to a generic performance counter pair or to an
implementation-dependent monitor. For generic performance counter pairs, overflow
status bit PMC[i/64]{i%64} corresponds to generic counter pair PMC[i]/PMD[i], where
4<=i<=p, and p is the index of the last implemented generic PMC/PMD pair.
There are currently two criteria for generating a performance monitor interrupt:
1. A generic performance counter pair (PMC[n]/PMD[n]) overflows and its overflow
interrupt bit (PMC[n].oi) is 1.
2. An implementation-dependent monitor wants to report an event with an
interruption.
If any of these criteria are met, the processor will:
• Set the corresponding overflow status bit in PMC[0]..PMC[3] to 1, and
• Raise a Performance Monitor interrupt, and
• Set the freeze bit (PMC[0].fr) which suspends event monitoring.
PMU interrupts are generated by events, such as the overflowing of a generic counter
pair which is configured to interrupt on overflow. Each such event generates one
interrupt. Provided that software does not clear the freeze bit, while either or both of
PSR.up and pp are 1, before clearing the overflow bits, writes to PMCs and PMDs by
software do not generate interrupts, nor cause a monitor which had generated an
interrupt to generate a second interrupt. (For overflow bits in PMC 0, even if either or
both of PSR.up and .pp are 1, software may clear the overflow bits and the freeze bit
with a single write to PMC 0 without causing any additional interrupts to be generated.)
Software may restore PMU state which has the freeze bit equal to 1 and one or more
overflow bits equal to 1 without generating any interrupts provided that it ensures
either that:
• both PSR.up and pp are zero during the restore, or
• the freeze bit is a 1 (and serialized) before any overflow bits are set to 1
When the PMU is disabled by writing a 0 into PSR.up and .pp and serializing this write,
the PMU cannot generate any interrupts and no SW writes to any PMU state can cause
any interrupts.
When a generic performance counter pair (PMC[n]/PMD[n]) overflows and its overflow
interrupt bit (PMC[n].oi) is 0, the corresponding overflow status register bit is set to 1.
However, in this case of counter overflow without interrupt, the freeze bit in the PMC[0]
is left unchanged, and event monitoring continues.
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indicate which monitor caused the interruption.
Volume 2, Part 1: Debugging and Performance Monitoring