Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 455
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Taken Branch Trap vector (0x5f00)
Name
Cause
A taken branch was executed, and the PSR.tb bit is 1. IA-32 instructions can not raise
this trap, IA-32 taken branch traps are delivered on the IA_32_Exception(Debug)
vector.
The Taken Branch trap is not taken on an rfi instruction.
Interruptions on this vector:
Taken Branch trap
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to
Note: Please see
for a further clarification of the IIP value for an unimplemented instruction
address trap or fault.
IIB0, IIB1 – If implemented, the IIB registers contain the instruction bundle pointed to
by IIPA. Please refer to
(IIB0-1 – CR26, 27)" on page 2:42
ISR – The ISR.ei bits are set to indicate which instruction caused the exception. The
ISR.code contains a bit vector (see
occurred in the just-executed instruction. The defined ISR bits are specified below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Volume 2, Part 1: Interruption Vector Descriptions
"Interruption Instruction Bundle Pointer (IIP – CR19)" on page 2:37
Section 3.3.5.10, "Interruption Instruction Bundle Registers
0
0
0
page 2:165
for a detailed description.
for details on the IIB registers.
Table 8-3 on page
2:170) for all traps which
0
0
8
7
6
5
4
3
2
0 0 0 ss 1 0 0
ei
0 ni ir 0 0 0 0 0 0
1
0
2:207
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