Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 591

Table 11-36. Synchronization Requirements for MOV-from-CPUID
vcpuid0-4
Table 11-37. Interruptions when MOV-from-CPUID Optimization is Enabled
MOV-from-CPUID
11.7.4.2.6 Cover Optimization
The cover optimization is enabled by the a_cover bit in the Virtualization Acceleration
Control (vac) field in the VPD. When this optimization is enabled, software running with
PSR.vm==1 will be able to execute cover instructions without any intercepts to the
VMM, unless a fault condition is detected (see
instruction will execute and vcr.ifs will be updated if vpsr.ic is 0.
If this optimization is disabled, execution of the cover instruction with PSR.vm==1
results in a virtualization intercept.
Synchronization is required when this optimization is enabled, see
details.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, "Virtual Processor Descriptor (VPD)" on page
Table 11-38. Synchronization Requirements for Cover Optimization
vifs
Table 11-39. Interruptions when Cover Optimization is Enabled
cover
11.7.4.2.7 Bank Switch Optimization
The bank switch optimization is enabled by the a_bsw bit in the Virtualization
Acceleration Control (vac) field in the VPD. When this optimization is enabled, execution
of the bsw instruction with PSR.vm==1 spills the currently active banked registers and
the corresponding NaT bits to the VPD, and loads the other banked registers and the
Volume 2, Part 1: Processor Abstraction Layer
Optimization
VPD Resource
Instructions
VPD Resource
Instructions
Synchronization Required
Write
Interruptions
When the MOV-from-CPUID optimization is enabled,
MOV-from-CPUID instructions with PSR.vm==1, may raise the fol-
lowing faults:
• Illegal Operation fault – if the target operand specifies GR 0 or
an out-of-frame stacked register
• Register NaT Consumption fault – if the NaT bit in the target
register is one
• Reserved Register/Field fault – if a reserved CPUID register is
being read
Table 11-39
Synchronization Required
Read, Write
Interruptions
When the cover optimization is enabled, cover instructions with
PSR.vm==1, may raise the following faults:
• Illegal Operation fault – if the instruction is not the last instruction
in an instruction group
for details). The cover
Table 11-38 for
2:326.
2:343