Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 588

Table 11-29. Interruptions when Virtual External Interrupt Optimization is
rsm, ssm
MOV-from-TPR
MOV-to-TPR
Note: This field cannot be enabled together with d_extint or d_psr_i virtualization dis-
ables. If this control is enabled together with any one of described disables, an
error will be returned during PAL_VP_CREATE and PAL_VP_REGISTER. See
Section 11.7.4.4, "Virtualization Optimization Combinations" on page 2:349
details.
11.7.4.2.2 Interruption Control Register Read Optimization
The interruption control register read optimization is enabled by the a_from_int_cr bit
in the Virtualization Acceleration Control (vac) field in the VPD. When this optimization
is enabled, and vpsr.ic is 0, software running with PSR.vm==1 will be able to read the
virtual interruption control registers (vipsr, visr, viip, vifa, vitir, viipa, vifs, viim, viha,
viib0-1) without any intercepts to the VMM, unless a fault condition is detected (see
Table 11-31
If this optimization is disabled, a read of the interruption CRs with PSR.vm==1 results
in a virtualization intercept.
Synchronization is required when this optimization is enabled, see
details.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, "Virtual Processor Descriptor (VPD)" on page
Table 11-30. Synchronization Requirements for Interruption Control Register
vipsr, visr, viip, vifa, vitir, viipa, vifs, viim, viha, viib0-1
2:340
Enabled
Instructions
When the virtual external interrupt optimization is enabled, execution
of rsm and ssm instructions with PSR.vm==1 which modify only
vpsr.i, may raise the following faults:
When the virtual external interrupt optimization is enabled, execution
of MOV-from-CR instruction targeting vtpr with PSR.vm==1, may
raise the following faults:
When the virtual external interrupt optimization is enabled, execution
of MOV-to-CR instruction targeting vtpr with PSR.vm==1, may raise
the following faults:
for details).
Read Optimization
VPD Resource
Interruptions
• Privileged Operation fault – if vpsr.cpl is not zero
• Illegal Operation fault – if the target operand specifies GR 0 or
an out-of-frame stacked register
• Privileged Operation fault – if vpsr.cpl is not zero
• Privileged Operation fault – if vpsr.cpl is not zero
• Register NaT Consumption fault – if the NaT bit in the source
register is one
• Reserved Register/Field fault – if the reserved field in the vtpr is
being written with a non-zero value
Write
Volume 2, Part 1: Processor Abstraction Layer
Table 11-30 for
2:326.
Synchronization Required
for