Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 285

Table 3-7.
Field
code
vector
x
w
r
na
sp
rs
ir
ni
so
ei
ed
rv
3.3.5.3 Interruption Instruction Bundle Pointer (IIP – CR19)
On an interruption and if PSR.ic is 1, the IIP receives the value of IP. IIP contains the
virtual address (or physical if instruction translations are disabled) of the next
instruction bundle or the IA-32 instruction to be executed upon return from the
interruption. For IA-32 instruction addresses, IIP is zero extended to 64-bits and
specifies a byte granular address. For traps and interrupts, IIP points to the next
instruction to execute. For faults, IIP points to the faulting instruction. As shown in
Volume 2, Part 1: System State and Programming Model
Interruption Status Register Fields
Bits
15:0 Interruption Code – 16 bit code providing additional information specific to the current
interruption. For IA-32 specific exceptions and software interrupts, contains the IA-32
interruption error code or zero.
23:16 IA-32 exception/interception vector number. For IA-32 exceptions and software
interrupts, contains the IA-32 vector number (e.g., GPFault has a vector number of
13). See Chapter 9, "IA-32 Interruption Vector Descriptions"
32 Execute exception – Interruption is associated with an instruction fetch (including
IA-32).
33 Write exception – Interruption is associated with a write operation. Both ISR.r and
ISR.w are set for IA-32 read-modify-write instructions.
34 Read exception – Interruption is associated with a read operation. Both ISR.r and
ISR.w are set for IA-32 read-modify-write instructions.
35 Non-access exception – See
Interruptions" on page
instruction set.
36 Speculative load exception – Interruption is associated with a speculative load
instruction. This bit is always 0 for interruptions taken in the IA-32 instruction set.
37 Register Stack – Interruption is associated with a mandatory RSE fill or spill. This bit is
always 0 for interruptions taken in the IA-32 instruction set.
38 Incomplete Register frame – The current register frame is incomplete when the
interruption occurred. This bit is always 0 for interruptions taken in the IA-32 instruction
set.
39 Nested Interruption – Indicates that PSR.ic was 0 or in-flight when the interruption
occurred. This bit is always 0 for interruptions taken in the IA-32 instruction set.
40 IA-32 Supervisor Override – Indicates the fault occurred during an IA-32 instruction set
supervisor override condition (the processor was performing a data memory accesses
to the IDT, GDT, LDT or TSS segments) or an IA-32 data memory access at a privilege
level of zero. This bit is always 0 for interruptions taken while executing Intel Itanium
instructions.
42:41 Excepting Instruction –
0 – exception due to instruction in slot 0
1 – exception due to instruction in slot 1
2 – exception due to instruction in slot 2
For faults and external interrupts, ISR.ei is equal to IPSR.ri. For traps, ISR.ei defines
the slot of the excepting instruction. Traps on the L+X instruction of an MLX set ISR.ei
to 2. This field is always 0 for interruptions taken in the IA-32 instruction set.
43 Exception Deferral – this bit is set to the value of the TLB exception deferral bit
(TLB.ed) for the instruction page containing the faulting instruction. If a translation
does not exist or instruction translation is disabled, or if the interruption is caused by a
mandatory RSE spill or fill, ISR.ed is set to 0. This bit is always 0 for interruptions taken
in the IA-32 instruction set.
31:24, reserved
63:44
Description
Section 5.5.2, "Non-access Instructions and
2:103. This bit is always 0 for interruptions taken in the IA-32
for details.
2:37