Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 362

Table 5-7.
Offset
0x5900
0x5a00
0x5b00
0x5c00
0x5d00
0x5e00
0x5f00
0x6000
0x6100
0x6200
0x6300
0x6400
0x6500
0x6600
0x6700
0x6800
0x6900
0x6a00
0x6b00
0x6c00
...
0x7f00
a. Unlike the other Reserved IVT vectors, which may defined in future revisions of the architecture, vector
0x5800 is permanently reserved. Software may use this vector for any purpose, such as placing in this area
portions of other handlers that don't fit into their assigned vector.
5.8 Interrupts
This section describes the programming model of the high performance interrupt
architecture. Interrupts are managed by the processor and by one or more intelligent
external interrupt controllers or devices in the I/O subsystem.
one example of a high performance interrupt architecture subsystem; other topologies
are possible. The processor is responsible for queuing and masking interrupts, sending
and receiving inter-processor interrupt (IPI) messages, receiving interrupt messages
from external interrupt controller(s), and managing local interrupt sources. This
document describes the processor's interrupt control mechanism only; for details on
external interrupt controllers or I/O devices refer to platform documentation.
2:114
Interruption Vector Table (IVT) (Continued)
Vector Name
Debug vector
Unaligned Reference vector
Unsupported Data Reference vector
Floating-point Fault vector
Floating-point Trap vector
Lower-Privilege Transfer Trap vector
Taken Branch Trap vector
Single Step Trap vector
Virtualization vector
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IA-32 Exception vector
IA-32 Intercept vector
IA-32 Interrupt vector
Reserved
Reserved
Reserved
Interruption(s) Page
18, 31, 62 2:200
63 2:201
70 2:202
71 2:203
73 2:204
72, 74 2:205
75 2:207
76 2:208
48 2:209
20, 21, 32, 41, 42, 2:210
49, 50, 64, 66, 67,
68, 79, 80, 82, 83,
84
33, 34, 65, 77, 78 2:211
81 2:212
Figure 5-3 shows just
Volume 2, Part 1: Interruptions