Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 593

There is no synchronization requirement for the virtualization of
11.7.4.2.9 Test Feature Optimization
The test feature optimization is enabled by the a_tf bit in the Virtualization Acceleration
Control (vac) field in the VPD.
When this optimization is enabled, test feature (tf) instructions running with
PSR.vm==1 will test the VCPUID[4] register in the VPD. The VMM may maintain a
different VCPUID[4]{63:32} value from the CPUID[4]{63:32} value of the logical
processor on which the virtual processor is running.
If the VMM indicates to a guest that an instruction is not supported by clearing the
corresponding bit in VCPUID[63:32], then guest execution of that instruction, when
a_tf is enabled, will behave the same as it would in implementations that do not
implement that instruction. See
Table 11-42.Impact of clearing VCPUID bits with the a_tf optimization
VCPUID[4] bit
If this optimization is disabled or not supported, execution of the test feature (tf)
instruction with PSR.vm==1 will test the CPUID[4] register. The VMM must maintain
the same VCPUID[4]{63:32} value as the CPUID[4]{63:32} value of the logical
processor on which the virtual processor is running.
Synchronization is required when this optimization is enabled; see
details.
This optimization is not supported on all processor implementations. Software can call
PAL_VP_ENV_INFO to determine the availability of this feature.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, "Virtual Processor Descriptor (VPD)" on page
Table 11-43.Synchronization Requirements for Test Feature Optimization
vcpuid[4]{63:32}
11.7.4.2.10 Interruption Collection and User Mask Optimization
The interruption collection and user mask optimization is enabled by the a_ic_um bit in
the Virtualization Acceleration Control (vac) field in the VPD.
When this optimization is enabled and PSR.vm==1, execution of rsm and ssm
instructions
not intercept to the VMM, unless a fault condition is detected (see
details). The ic field in vpsr and user mask bits in PSR targeted by the mask will be
updated with the new value.
Volume 2, Part 1: Processor Abstraction Layer
Table 11-42
Instructions affected
32
33
VPD Resource
1
with a mask targeting no fields other than the ic and user mask fields will
for more information.
clz
mpy4
mpyshl4
Synchronization Required
Write
instructions.
probe
Behavior when vCPUID[4] is bit is 0
Illegal Operation fault
Illegal Operation fault
Illegal Operation fault
Table 11-43
2:326.
Table 11-45
for
for
2:345