Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 852

10.2 Configuration of External Interrupt Vectors
As defined in
from one of four sources:
• From external sources, e.g. external interrupt controllers or intelligent external I/O
devices, or
• From the processor's LINT0 or LINT1 pins
compatible interrupt controller), or
• From internal processor sources, e.g. timers or performance monitors, or
• From other processors, e.g. inter-processor interrupts (IPIs).
All interrupts are point-to-point communications. There is no facility for broadcasting of
interrupts. The interrupt message protocol used by the processor-to-processor and the
external source-to-processor is not defined architecturally, and is not visible to
software.
A number of external interrupt control registers (LID,TPR, ITV, PMV, CMCV, LRR0 and
LRR1) allow software to directly configure the processor interrupt resources. The Local
ID register (LID) establishes a processor's unique physical interrupt identifier. The Task
Priority Register (TPR) allows masking of external interrupts based on vector priority
classes. The ITV, PMV, CMCV, LRR0 and LRR1 external interrupt control registers
configure the vector number for the processor's local interrupt sources. Configuration of
the external controllers and devices is controller-/device-specific, and is beyond the
scope of this document.
10.3 External Interrupt Masking
The Itanium architecture provides four mechanisms to prevent external interrupts from
being delivered to a processor: a bit in the processor status register (PSR.i), the
interrupt vector register (IVR) and the end-of-interrupt (EOI) register, the task priority
register (TPR), and the external task priority register (XTPR). The next four sections
discuss these mechanisms.
10.3.1 PSR.i
When PSR.i is zero, the processor does not accept any external interrupts. However,
interrupts continue to be pended by the processor. Software can use PSR.i to
temporarily disable taking of external interrupts, e.g. to ensure uninterruptable
execution of critical code sections. Since clearing of PSR.i takes effect immediately
(refer to the rsm instruction page), software is not necessarily required to explicitly
serialize clearing of PSR.i (unless another processor resource requires serialization). On
1. Processors optionally support two external interrupt pins. Software can query for the presence of
LINT pins via the PAL_PROC_GET_FEATURES procedure call.
2:604
Section 5.8, "Interrupts" on page 2:114, external interrupts originate
1
(typically connected to an Intel 8259A
Volume 2, Part 2: External Interrupt Architecture