Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 603

Table 11-49.PAL Cache and Memory Procedures (Continued)
Procedure
PAL_CACHE_PROT_INFO
PAL_CACHE_SHARED_INFO
PAL_CACHE_SUMMARY
PAL_MEM_ATTRIB
PAL_PREFETCH_VISIBILITY
PAL_PTCE_INFO
PAL_VM_INFO
PAL_VM_PAGE_SIZE
PAL_VM_SUMMARY
PAL_VM_TR_READ
a. Calling this procedure may affect resources on multiple processors. Please refer to implementation-specific reference manuals
for details.
Table 11-50.PAL Processor Identification, Features, and Configuration Procedures
Procedure
PAL_BRAND_INFO
PAL_BUS_GET_FEATURES
PAL_BUS_SET_FEATURES
PAL_DEBUG_INFO
PAL_FIXED_ADDR
PAL_FREQ_BASE
PAL_FREQ_RATIOS
PAL_GET_HW_POLICY
PAL_LOGICAL_TO_PHYSICAL
PAL_PERF_MON_INFO
a
PAL_PLATFORM_ADDR
PAL_PROC_GET_FEATURES
Volume 2, Part 1: Processor Abstraction Layer
Idx Class Conv.
38 Req. Static
43 Opt. Static
4 Req. Static
5 Req. Static
41 Req. Static
6 Req. Static
7 Req. Static
34 Req. Static
8 Req. Static
261 Req. Stacked
Idx Class Conv.
274 Opt. Stacked
9 Req. Static
a
10 Req. Static
11 Req. Static
12 Req. Static
13 Opt. Static
14 Req. Static
48 Opt. Static
42 Opt. Static
15 Req. Static
16 Req. Static
17 Req. Static
Mode Buffer
Both No Return instruction or data cache protection
information.
Both No Returns information on which logical processors
share caches.
Both No Return a summary of the cache hierarchy.
Both No Return a list of supported memory attributes.
Both No Used in architected sequence to transition
pages from a cacheable, speculative attribute to
an uncacheable attribute. See
"Physical Addressing Attribute Transition –
Disabling Prefetch/Speculation and Removing
Cacheability" on page
Both No Return information needed for ptc.e
instruction to purge entire TC.
Both No Return detailed information about virtual
memory features supported in the processor.
Both No Return virtual memory TC and hardware walker
page sizes supported in the processor.
Both No Return summary information about virtual
memory features supported in the processor.
Phys. No Read contents of a translation register.
Mode Buffer
Both No Provides processor branding information.
Phys. No Return configurable processor bus interface
features and their current settings.
Phys. No Enable or disable configurable features in
processor bus interface.
Both No Return the number of instruction and data
breakpoint registers.
Both No Return the fixed component of a processor's
directed address.
Both No Return the frequency of the output clock for use
by the platform, if generated by the processor.
Both No Return ratio of processor, bus, and interval time
counter to processor input clock or output clock
for platform use, if generated by the processor.
Both Dep. Get current hardware resource sharing policy.
Both No Return information on which logical processors
map to a physical processor package.
Both No Return the number and type of performance
monitors.
Both No Specify processor interrupt block address and
I/O port space address.
Phys. No Return configurable processor features and
their current setting.
Description
Section 4.4.11.2,
2:90.
Description
2:355