Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 461

IA-32 Interruption Vector Descriptions
This section gives detailed description of all possible IA-32 exceptions, interrupts and
intercepts that can occur during IA-32 instruction set execution in the Itanium System
Environment. Interruption resources not noted below are undefined after the
interruption. For all cases where an interruption is taken out of the IA-32 instruction
set, IPSR.is is set to 1.
9.1 IA-32 Trap Code
The following trap code is defined for concurrent traps reported during IA-32 instruction
set execution. There is a bit for every possible concurrent trap condition.
Figure 9-1.
15 14 13 12 11 10 9
Figure 9-2.
Bit
2 tb
3 ss
4-7 b0 to b3
9.2 IA-32 Interruption Vector Definitions
Following are the definitions of IA-32 exceptions, interrupts and intercepts that can
occur during IA-32 instruction set execution in the Itanium system environment.
Volume 2, Part 1: IA-32 Interruption Vector Descriptions
IA-32 Trap Code
8 7 6 5 4
0 b3 b2 b1 b0 ss tb
IA-32 Trap Code
Name
taken branch trap, set if an IA-32 branch is taken and branch traps are enabled
(PSR.tb is 1).
single step trap, set after the successful execution of every IA-32 instruction if PSR.ss
or EFLAG.tf is 1.
Data breakpoint trap due to a match with the corresponding Intel Itanium data
breakpoint registers. Each bit indicates a match with the corresponding DBR
registers; b0=DBR0/1, b1=DBR2/3, b2=DBR4/5, b3=DBR6/7. Zero, one or more bits
may be set. These bits accumulate data breakpoint register matches that occurred
during the duration of executing one IA-32 instruction. In order to be reported, the
DBR register address and mask registers must precisely match the IA-32 data
memory reference address, and the DBR read, write bits match the type of memory
transaction, and the DBR privilege level mask match the value in PSR.cpl.
3 2 1 0
0
Description
9
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