Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 381

Register Stack Engine
The register stack engine (RSE) moves registers between the register stack and the
backing store in memory without explicit program intervention. The RSE operates
concurrently with the processor and can take advantage of unused memory bandwidth
to dynamically issue register spill and fill operations. In this manner, the latency of
register spill/fill operations can be overlapped with useful program work. The basic
principles of the register stack are discussed in
page 1:47. This chapter presents the internal state, the programming model and the
interruption behavior of the register stack engine.
6.1 RSE and Backing Store Overview
The register stack frames are mapped onto a set of physical registers which operate as
a circular buffer containing the most recently created frames. The RSE spills and fills
these physical registers to/from a backing store in memory. The RSE moves registers
between the physical register stack and the backing store without explicit program
intervention. As indicated in
registers outside of the currently active frame (as defined by CFM). These registers
contain the frames of the parent procedures of the current procedure.
As shown in
from lower to higher addresses. The Backing Store Pointer (BSP) application register
contains the address of the first (lowest) memory location reserved for the current
frame (i.e., the location at which GR32 of the current frame will be spilled). RSE spill/fill
activity occurs at addresses below what is contained in the BSP since the RSE spills/fills
the frames of the current procedure's parents. The BSPSTORE application register
contains the address at which the next RSE spill will occur. The address register which
corresponds to the next RSE fill operation, the BSP load pointer, is not architecturally
visible. The addresses contained in BSP and BSPSTORE are always aligned to an 8-byte
boundary. The backing store contains the local area of each frame. The output area is
not spilled to the backing store (unless it later becomes part of a callee's local area).
Within each stack frame, lower-addressed registers are stored at lower memory
addresses. RSE spills of NaTed stacked general registers are subject to the same
memory update constraints as software spills (st8.spill) of NaTed static general
registers (see
The RSE also spills/fills the NaT bits corresponding to the stacked registers. The NaT
bits corresponding to the static subset must be spilled/filled as necessary by software.
The NaT bits are the 65th bit of each general register. The NaT bits for the stacked
subset are spilled/filled in groups of 63 corresponding to 63 consecutive physical
stacked registers. When the RSE spills a register to the backing store the corresponding
NaT bit is copied to the RSE NaT collection (RNAT) application register. Whenever bits
8:3 of BSPSTORE are all ones, the RSE stores RNAT to the backing store. As shown in
Figure 6-2, this results in a backing store memory image in which every 63 register
values are followed by a collection of NaT bits. Bit 0 of the NaT collection corresponds to
the first (lowest addressed) of the 63 register values; bit 62 corresponds to the 63rd
register value. Bit 63 of the NaT collection is always written as zero. When the RSE fills
Volume 2, Part 1: Register Stack Engine
Figure
Figure 6-1, the backing store is organized as a stack in memory that grows
"Register Spill and Fill" on page
Section 4.1, "Register Stack" on
6-1, the RSE operates on the physical stacked
1:62).
6
2:133