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PAL_CACHE_INFO
PAL_CACHE_INFO – Get Detailed Cache Information (2)
Returns information about a particular processor instruction or data cache at a specified
Purpose:
level in the cache hierarchy.
Static Registers Only
Calling Conv:
Physical and Virtual
Mode:
Not dependent
Buffer:
Arguments:
Argument
index
cache_level
cache_type
Reserved
Returns:
Return Value
status
config_info_1
config_info_2
Reserved
Status:
Status Value
0
-2
-3
This call describes in detail the characteristics of a given processor controlled cache in
Description:
the cache hierarchy. It returns information in the config_info_1 and config_info_2
returns parameters.
The config_info_1 return value has the following structure:
Figure 11-2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
stride
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
load_hints
• u
Bit that is 1 if the cache is unified and 0 if the cache is split.
• at - 2-bit field denoting cache memory attributes, as follows:
Table 11-67. Cache Memory Attributes
Value
0
Write through cache
1
Write back cache
2-3
Reserved
• associativity
value of 0 indicates a fully associative cache. A value of 1 indicates a direct mapped
cache.
• line_size
minimum write back size of a flush operation to memory or the line size of the
2:374
Description
Index of PAL_CACHE_INFO within the list of PAL procedures.
Unsigned 64-bit integer specifying the level in the cache hierarchy for which information is
requested. This value must be between 0 and one less than the value returned in the
cache_levels return value from PAL_CACHE_SUMMARY.
Unsigned 64-bit integer with a value of 1 for instruction cache and 2 for data or unified cache.
All other values are reserved.
0
Description
Return status of the PAL_CACHE_INFO procedure.
The format of config_info_1 is shown in
The format of config_info_2 is shown in
0
Description
Call completed without error
Invalid argument
Call completed with error
config_info_1 Return Value
line_size
store_hints
Description
Unsigned 8-bit integer denoting the associativity of the cache. A
Unsigned 8-bit integer denoting the binary logarithm (log2) of the
Figure
11-2.
Figure
11-3.
8
7
6
associativity
reserved
load_latency
Volume 2, Part 1: Processor Abstraction Layer
5
4
3
2
1
0
at
u
store_latency

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