Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 349

• If more than one trap is triggered (such as Unimplemented Instruction Address
trap, Lower-Privilege Transfer trap, and Single Step trap) the highest priority
trap is taken. The ISR.code contains a bit vector with one bit set for each trap
triggered.
A sequential execution model is presented in the preceding description.
Implementations are free to use a variety of performance techniques such as pipelined,
speculative, or out-of-order execution provided that, to the programmer, the illusion
that instructions are executed sequentially is preserved.
5.4 PAL-based Interruption Handling
PAL-based interruption handling requires the processor to transfer control to the PAL
firmware. The PAL firmware will execute handling code and set up the architected exit
state before transferring control to the SAL firmware. See
Abstraction Layer"
SAL firmware layers for PAL-based interruption handling.
It is strongly recommended that software ensure that, if machine check aborts are
masked (PSR.mc), external interrupts are also masked (PSR.i). This will avoid cases
where a corrected machine check interrupt (a lower priority interrupt) is handled before
a machine check abort, which would cause an escalation in machine check abort
severity when machine check aborts are unmasked.
5.5 IVA-based Interruption Handling
IVA-based interruption handling is implemented as a fast context switch. On IVA-based
interruptions, instruction and data translation is left unchanged, the endian mode is set
to the system default, and delivery of most PSR-controlled interruptions is disabled
(including delivery of asynchronous events such as external interrupts). The processor
is responsible for saving only a minimal amount of state in the interruption resource
registers prior to vectoring to the Itanium architecture-based software handler.
When an interruption occurs, the processor takes the following actions:
1. If PSR.ic is 0:
• IPSR, IIP, IIPA, IIB0-1, and IFS.v are unchanged.
• Interruption-specific resources IFA, IIM, and IHA are unchanged.
If PSR.ic is 1:
• PSR is saved in IPSR. If PSR is in-flight, IPSR will get the most recent in-flight
value of PSR (i.e., PSR is serialized by the processor before it is written into
IPSR). For Itanium traps, the value written to IPSR.ri is the next instruction slot
that would have been executed if there had been no trap. For all other
interruptions, the value written to IPSR.ri is the instruction slot on which the
interruption occurred (1 for interruptions on the L+X instruction of an MLX). For
interruptions in the IA-32 instruction set, IPSR.ri is set to 0.
• IP is written into IIP. For faults and external interrupts, the saved IP is the IP at
which the interruption occurred. For traps, the saved IP is the value after the
execution of the IA-32 or Itanium instruction which caused the trap. For
Volume 2, Part 1: Interruptions
for more details on the architected exit state between the PAL and
Chapter 11, "Processor
2:101