Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 299

4.1.1.4 Purge Behavior of TLB Inserts and Purges
Translations contained in the translation caches (TC) and translation registers (TR) are
maintained in a consistent state by ensuring that TLB insertions remove existing
overlapping entries before new TR or TC entries are installed. Similarly, TLB purges that
partially or fully overlap with existing translations may remove all overlapping entries.
In this context, "overlap" refers to two translations with the same region identifier (but
not necessarily identical virtual region numbers), and with partially or fully overlapping
virtual address ranges (determined by the virtual address and the page size). Examples
are: two 4K-byte pages at the same virtual address, or an 8K-byte page at virtual
address 0x2000 and a 4K-byte page at 0x3000.
As described in
VRN field, and virtual address bits {63:61} may be used as part of the match for
memory references (references other than inserts and purges). This binding of a
translation to the VRN implies that a lookup of a given virtual address (region
identifier/VPN pair) in either the translation cache or translation registers may result in
a TLB miss if a memory reference is made through a different VRN (even if the region
identifiers in the two region registers are identical). Some processor models may also
omit the VRN field of the TLB, causing the TLB search on memory references to find an
entry independent of VRN bits. However, all processor models are required, during
translation cache purge and insert operations, to purge all possible translations
matching the region identifier and virtual address regardless of the specified VRN.
Figure 4-4.
Hash
A processor may overpurge translation cache entries; i.e., it may purge a larger virtual
address range than required by the overlap. Since page sizes are powers of 2 in size
and aligned on that same power of 2 boundary, purged entries can either be a superset
of, identical to, or a subset of the specified purge range.
Table 4-1
Table 4-2
Volume 2, Part 1: Addressing and Protection
Section 4.1, "Virtual Addressing" on page
Conceptual Virtual Address Searching for Inserts and Purges
Region
Registers
rr
0
rr
1
rr
2 Region ID
rr
7
24
search
Region ID Key VRN
Translation Lookaside Buffer (TLB)
define the purge behavior of different TLB insert and purge instructions.
describes the purge behavior for VHPT inserts.
63 61 60
3
Virtual Region Number (VRN)
search
Virtual Page Num (VPN) Rights
2:45, each TLB may contain a
Virtual Address
Virtual Page Number (VPN)
Physical Page Num (PPN)
0
2:51