Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 696

PAL_PROC_GET_FEATURES
Table 11-112. Processor Features (Continued)
Bit Class Control Scope
54 Opt.
53 Opt.
52 Opt.
51:48 N/A
47 Opt.
46 Opt
45 Opt.
44 Opt.
43 Opt.
42 Opt.
41 Opt.
2:448
Req. No Enable the use of the vmsw instruction. When 0, the vmsw instruction
causes a Virtualization fault when executed at the most privileged level.
When 1, this bit will enable normal operation of the vmsw instruction. This bit
has no effect if virtual machine features are disabled (see bit 40).
Req. May Enable MCA signaling on unconsumed data-poisoning event detection.
When 0, a CMCI will be signaled on error detection. When 1, an MCA will be
signaled on error detection. Note that the reported error severity depends on
which method is chosen for signaling; see
Data-Poisoning Event Handling"
then the corresponding argument is ignored when calling
PAL_PROC_SET_FEATURES. Note that the functionality of this bit is
independent of the setting in bit 60 (Enable CMCI promotion), and that the
bit 60 setting does not affect CMCI signaling for data-poisoning related
events.
Req. May Disable P-states. Provides the ability to disable p-states when they are
implemented by the processor. When the feature is available and status is 1
or when the feature is not available, the PAL P-state procedures
(PAL_PSTATE_INFO, PAL_SET_PSTATE, PAL_GET_PSTATE) will return
with a status of -1 (Unimplemented procedure). When the feature is
available and the status is 0, the PAL P-state procedures will operate
normally.
N/A N/A Reserved
Opt. May Disable Dynamic branch prediction. When 0, the processor may predict
branch targets and speculatively execute, but may not commit results. When
1, the processor must wait until branch targets are known to execute.
Opt. May Disable Dynamic Instruction Cache Prefetch. When 0, the processor may
prefetch into the caches any instruction which has not been executed, but
whose execution is likely. When 1, instructions may not be fetched until
needed or hinted for execution. (Prefetch for a hinted branch is allowed even
when dynamic instruction cache prefetch is disabled.)
Opt. May Disable Dynamic Data Cache Prefetch. When 0, the processor may prefetch
into the caches any data which has not been accessed by instruction
execution, but which is likely to be accessed. When 1, no data may be
fetched until it is needed for instruction execution or is fetched by an lfetch
instruction.
Req. No Disable Spontaneous Deferral. When 1, the processor may optionally defer
speculative loads that do not encounter any exception conditions, but that
trigger other implementation-dependent conditions (e.g., cache miss). This
behavior is gated by the programming model described in
"Deferral of Speculative Load Faults" on page
deferral is disabled.
Opt. No Disable Dynamic Predicate Prediction. When 0, the processor may predict
predicate results and execute speculatively, but may not commit results until
the actual predicates are known. When 1, the processor shall not execute
predicated instructions until the actual predicates are known.
c
No RO XR1 through XR3 implemented. Denotes whether XR1 - XR3 are
implemented for machine check recovery. This feature may only be
interrogated by PAL_PROC_GET_FEATURES. It may not be enabled or
disabled by PAL_PROC_SET_FEATURES. The corresponding argument is
ignored.
No RO XIP, XPSR, and XFS implemented. Denotes whether XIP, XPSR, and XFS
are implemented for machine check recovery. This feature may only be
interrogated by PAL_PROC_GET_FEATURES. It may not be enabled or
disabled by PAL_PROC_SET_FEATURES. The corresponding argument is
ignored.
Description
Section 11.3.2.3, "Unconsumed
for details.If this feature is not supported,
Section 5.5.5,
2:105. When 0, spontaneous
Volume 2, Part 1: Processor Abstraction Layer