Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 673

Table 11-97. err_struct_info – Cache (Continued)
Field
cl_id
cl_dp
Reserved
tiv
trigger
trigger_pl
Reserved
Figure 11-28. capabilities vector for cache
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
Table 11-98. capabilities vector for cache
Field
i
d
rv
Volume 2, Part 1: Processor Abstraction Layer
Bits
8:6 Indicates which mechanism is used to identify the cache line to be used for error
injection:
0 – Reserved
1 – Virtual address provided in the inj_addr field of the buffer pointed to by
err_data_buffer should be used to identify the cache line for error injection.
2 – Physical address provided in the inj_addr field of the buffer pointed to by
err_data_buffershould be used to identify the cache line for error injection.
3 – way and index fields provided in err_data_buffer should be used to identify the cache
line for error injection.
All other values are reserved.
9 When 1, indicates that a multiple bit, non-correctable error should be injected in the
cache line specified by cl_id. If this injected error is not consumed, it may eventually
cause a data-poisoning event resulting in a corrected error signal, when the associated
cache line is cast out (implicit or explicit write-back of the cache line). The error severity
specified by err_sev in err_type_info must be set to 0 (corrected error) when this bit is
set.
31:10 Reserved
32 When 1, indicates that the trigger information fields (trigger, trigger_pl) are valid and
should be used for error injection. When 0, the trigger information fields are ignored and
error injection is performed immediately.
36:33 Indicates the operation type to be used as the error trigger condition. The address
corresponding to the trigger is specified in the trigger_addr field of the buffer pointed to
by err_data_buffer:
0 – Instruction memory access. The trigger match conditions for this operation type are
similar to the IBR address breakpoint match conditions as outlined in
"Debug Address Breakpoint Match Conditions" on page
1 – Data memory access. The trigger match conditions for this operation type are similar
to the DBR address breakpoint match conditions as outlined in
Address Breakpoint Match Conditions" on page
All other values are reserved.
39:37 Indicates the privilege level of the context during which the error should be injected:
0 – privilege level 0
1 – privilege level 1
2 – privilege level 2
3 – privilege level 3
All other values are reserved.
If the implementation does not support privilege level qualifier for triggers (i.e. if
trigger_pl is 0 in the capabilities vector), this field is ignored and triggers can be taken at
any privilege level.
63:40 Reserved
Reserved
Reserved
Bits
0 Error injection for instruction caches is supported
1 Error injection for data caches is supported
2 Reserved
PAL_MC_ERROR_INJECT
Description
2:154.
2:154.
8 7 6 5
wi va pa Reserved dp mesi data tag rv
37
Description
Section 7.1.2,
Section 7.1.2, "Debug
4 3 2 1 0
d i
36 35 34 33 32
trigger_pl trigger
2:425