Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 751

About the System Programmer's Guide
Part II: System Programmer's Guide is intended as a companion section to the
information presented in
crisp and concise architectural definition of the Itanium instruction set, Part II provides
insight into programming and usage models of the Itanium system architecture. This
section emphasizes how the various architecture features fit together and explains how
they contribute to high performance system software.
The intended audience for this section is system programmers who would like to better
understand the Itanium system architecture. The goal of this document is to:
• Familiarize system programmers with Itanium system architecture principles and
usage models.
• Provide recommendations, code examples, and performance guidelines.
This section does not re-define the Itanium instruction set. Please refer to
I:, "System Architecture Guide"
architecture.
The reader is expected to be familiar with the contents of Part I and is expected to be
familiar with modern virtual memory and multiprocessing concepts. Furthermore, this
document is platform architecture neutral (i.e. no assumptions are made about
platform architecture capabilities, such as busses, chipsets, or I/O devices).
1.1 Overview of the System Programmer's Guide
The Itanium architecture provides numerous performance enhancing features of
interest to the system programmer. Many of these instruction set features focus on
reducing overhead in common situations. The chapters outlined below discuss different
aspects of the Itanium system architecture.
Chapter 2, "MP Coherence and Synchronization"
multiprocessing synchronization primitives and the Itanium memory ordering model.
This chapter also discusses programming rules for self- and cross-modifying code. This
chapter is useful for application and system programmers who write multi-threaded
code.
Chapter 3, "Interruptions and Serialization"
despite its explicitly parallel instruction execution semantics, provides the system
programmer with a precise interruption model. This chapter describes how the
processor serializes execution around interruptions and what state is preserved and
made available to low-level system code when interruptions are taken. This chapter
introduces the interrupt vector table and describes how low-level kernel code is
expected to transfer control to higher level operating system code written in a
high-level programming language. This chapter is useful for operating system and
firmware programmers.
Volume 2, Part 2: About the System Programmer's Guide
Part I:, "System Architecture
as the authoritative definition of the system
discusses how the Itanium architecture,
Guide". While Part I provides a
describes Itanium architecture-based
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Part
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