Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 786

• When an external or independent agent (I/O device, timer, another processor)
requires attention from the processor, an interrupt occurs. There are several types
of interrupts. An initialization interrupt occurs when the processor has received an
initialization request. A Platform Management Interrupt (PMI) can be generated
by the platform to request features such as power management. Initialization
interrupts and PMIs are PAL-based interruptions. An external interrupt occurs
when an agent in the system requires the OS to perform some service on its behalf.
External interrupts are IVA-based interruptions. Interrupts are delivered
asynchronously with respect to program execution. The instruction upon which an
interrupt is delivered may or may not be related to the interrupt itself.
• An abort is generated by the processor when a malfunction (Machine Check) is
detected, or when a processor reset occurs. Aborts are asynchronous with respect
to program execution. If caused by a particular instruction, an abort may be
delivered sometime after that instruction completes. Aborts are PAL-based
interruptions.
An interruption handler returns from interruption when it executes an rfi instruction.
The rfi instruction copies state from specific control registers known as interruption
registers into their corresponding architectural state (e.g. IIP is copied into IP and
execution begins at that instruction address). Whether or not the state that is restored
by the rfi is the same state that was captured when the interruption occurred is up to
the operating system.
3.2 Interruption Vector Table
The Interruption Vector Address (IVA) control register defines the base address of the
interruption vector table (IVT). Each IVA-based interruption has its own architected
offset into this table as defined in
page 2:113. For the remainder of this section, "interruption" refers to an IVA-based
interruption, unless otherwise noted.
When an interruption occurs, the processor stops execution at the current IP, sets the
current privilege level to 0, and begins fetching instructions from the address of the
entry point to the interruption handler for the particular interruption that occurred. The
address of this entry point is defined by the base address of the IVT contained in the
IVA register and the architected offset into the table according to the interruption that
occurred.
The IVT is 32Kbytes long and contains the code for the interruption handlers. Execution
of the interruption handler begins at the entry point. The interruption handler may be
contained entirely in the IVT, or the handler may branch to code outside the IVT if more
space is needed.
When an interruption occurs, if the processor is operating with instruction address
translation enabled (PSR.it is 1), then the address in IVA is treated as a virtual address;
otherwise, it is treated as a physical address. Whenever an interruption may occur (i.e.
whenever external interrupts are not masked or disabled, or whenever an instruction
may raise a fault or trap), the software must ensure that the processor can safely
reference the IVT. As a result, the IVT must be permanently resident in physical
memory. If instruction address translation is enabled, the IVT must be mapped by an
instruction translation register and must point at a valid physical page frame. When
2:538
Section 5.7, "IVA-based Interruption Vectors" on
Volume 2, Part 2: Interruptions and Serialization