Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 291

• An interruption selects bank 0,
• rfi switches to the bank specified by IPSR.bn, or
• bsw switches to the specified bank.
On an interruption or bank switch, the processor ensures all prior register accesses
(reads and writes) are performed to the prior register bank. Data values in banked
registers are preserved across bank switches and both banks maintain NaT values when
loaded from general registers. Registers from both banks cannot be addressed at the
same time. However, non-banked general registers (GR0-15, and GR32-127) are
accessible regardless of the state of PSR.bn.
Figure 3-18.
Whether the ALAT register target tracking mechanism (see
page 1:63) distinguishes between the two register banks is implementation dependent;
from the ALAT's perspective, GR16 in bank 0 may be the same register as GR16 in bank
1 in some implementations.
Operating systems should ensure that IA-32 and Itanium architecture-based
application code is executed within register bank 1. If IA-32 or Itanium
architecture-based application code executes out of register bank 0, the application
register state (including IA-32) will be lost on any interruption. During interruption
processing the operating system uses register bank 0 as the initial working register
context.
Usage of these additional registers is determined by software conventions. However,
registers GR24 to GR31, of bank 0, are not preserved when PSR.ic is 1; operating
system code can not rely on register values being preserved unless PSR.ic is 0. While
PSR.ic is 1, processor-specific firmware may use these registers for machine check or
firmware interruption handling at any point regardless of the state of PSR.i. If PSR.ic is
0, GR24 to GR31 can be used as scratch registers for low-level interruption handlers.
Registers GR16 to GR23 are always preserved; operating system code can rely on the
values being preserved.
Volume 2, Part 1: System State and Programming Model
Banked General Registers
General Registers NaTs
63 0
gr
0
0
gr
1
gr
16
gr
31
gr
32
gr
127
0
Banked General
Registers
63 0
Volatile Registers
"Data Speculation" on
NaTs
0
gr
16
gr
23
gr
24
gr
31
2:43