Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 557

Table 11-12. Processor State Parameter Fields (Continued)
Field
us 9
hd 10
tl 11
mi 12
pi 13
pm 14
dy 15
in 16
rs 17
cm 18
ex 19
cr 20
pc 21
dr 22
tr 23
rr 24
ar 25
br 26
pr 27
fp 28
b1 29
b0 30
gr 31
dsize 47:32
se 48
rsvd 58:49
cc 59
tc 60
bc 61
Volume 2, Part 1: Processor Abstraction Layer
INIT
Bits
value
0 Uncontained storage damage. A value of 1 indicates the error is contained within the
CPU and memory hierarchy, but that some memory locations may be corrupt. If us is
set to 1, then co and sy will always be cleared to 0. See
0 Hardware damage. A value of 1 indicates that as a result of the machine check some
non essential hardware is no longer available causing this processor to execute with
degraded performance (no functionality has been lost).
0 Trap lost. A value of 1 indicates the machine check occurred after an instruction was
executed but before a trap that resulted from the instruction execution could be
generated.
0 More information. A value of 1 indicates that more error information about the
machine check event is available by making the PAL_MC_ERROR_INFO procedure
call.
0 Precise instruction pointer. A value of 1 indicates that the machine logged the
instruction pointer to the bundle responsible for generating the machine check.
0 Precise min-state save area. A value of 1 indicates that the min-state save area
contains the state of the machine for the instruction responsible for generating the
machine check. When this bit is set, the pi bit will always be set as well.
a
x Processor Dynamic State is valid. (1=valid, 0=not valid) See the
PAL_MC_DYNAMIC_STATE procedure call for more information.
1 Interruption caused by INIT. (0=machine check, 1=INIT)
a
x The RSE is valid. (1=valid, 0=not valid)
0 The machine check has been corrected. (1=corrected, 0=not corrected)
0 A machine check was expected. (1=expected, 0=not expected)
a
x Control registers are valid. (1=valid, 0=not valid)
a
x Performance counters are valid. (1=valid, 0=not valid)
a
x Debug registers are valid. (1=valid, 0=not valid)
a
x Translation registers are valid. (1=valid, 0=not valid)
a
x Region registers are valid. (1=valid, 0=not valid)
a
x Application registers are valid. (1=valid, 0=not valid)
a
x Branch registers are valid. (1=valid, 0=not valid)
a
x Predicate registers are valid. (1=valid, 0=not valid)
a
x Floating-point registers are valid. (1=valid, 0=not valid)
a
x Preserved bank one general registers are valid. (1=valid, 0=not valid)
a
x Preserved bank zero general registers are valid. (1=valid, 0=not valid)
a
x General registers are valid. (1=valid, 0=not valid) (does not include banked registers)
a
x Size in bytes of Processor Dynamic State returned by PAL_MC_DYNAMIC_STATE.
0 Shared Error. Machine check corresponds to structure shared by multiple logical
processors.
Reserved
0 Cache check. A value of 1 indicates that a cache related machine check occurred.
See the PAL_MC_ERROR_INFO procedure call for more information.
0 TLB check. A value of 1 indicates that a TLB related machine check occurred. See
the PAL_MC_ERROR_INFO procedure call for more information.
0 Bus check. A value of 1 indicates that a bus related machine check occurred. See the
PAL_MC_ERROR_INFO procedure call for more information.
Description
Table 11-8.
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