Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 560

Table 11-15. PMI Message Vector Assignments
Priority
Low
High
11.5.2 PALE_PMI Exit State
The state of the processor on exiting PALE_PMI is:
• GRs: The contents of non-banked general registers are unchanged from the time of
the interruption.
• Bank 1 GRs: The contents of all bank one general registers are unchanged from
the time of the interruption.
• Bank 0:GR16-23: The contents of these bank zero general registers are
unchanged from the time of the interruption.
• Bank 0:GR24-31: contain parameters which PALE_PMI passes to SALE_PMI:
• FRs: The contents of all floating-point registers are unchanged from the time of the
interruption.
• Predicates: The contents of all predicate registers are undefined and available for
use.
• BRs: The contents of all branch registers are unchanged, except the following which
contain the defined state.
• BR1 is undefined and available for use.
2:312
Vector
4
5
6
7
8 PAL Reserved
9
10
11
12
13 IA-32 Machine Check Rendezvous
14 PAL Reserved
15
• GR24 contains the value decoded as follows:
• Bits 7-0: PMI Vector Number
• Bit 63-8: Reserved
• GR25 contains the value of the min-state save area address stored in XR0.
• GR26 contains the value of saved RSC. The contents of this register shall be
preserved by SAL PMI handler.
• GR27 contains the value of saved B0. The contents of this register shall be
preserved by SAL PMI handler.
• GR28 contains the value of saved B1. The contents of this register shall be
preserved by SAL PMI handler.
• GR29 contains the value of the saved predicate registers. The contents of
this register shall be preserved by SAL PMI handler
• GR30-31 are scratch registers available for use.
Description
Volume 2, Part 1: Processor Abstraction Layer