Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 368

The processor provides nested interrupt priority support for external interrupt vectors
0, 2, and 16 through 255 by:
• Automatically masking external interrupts of equal or lower priority than the
highest priority external interrupt currently in-service. This raises the in-service
external interrupt masking level when each external interrupt begins service by an
IVR read.
• Associating EOI writes with the highest priority in-service external interrupt, and
removing the in-service indication for this external interrupt. This lowers the
in-service masking level to that of the next highest priority currently in-service
external interrupt (if any).
This mechanism allows software external interrupt handlers to be interrupted by higher
priority external interrupts.
For example, assume software acquires an external interrupt vector 45 by reading IVR.
During the service of this interrupt other external interrupts can still be received and
are pended. If software sets PSR.i to a 1, pending external interrupts of equal or lower
priority than 45 are masked. However, a higher priority pending external interrupt can
be accepted by the processor (provided it is not masked by TPR.mmi or TPR.mic).
Assuming external interrupt vector 80 is received by the processor, the processor will
accept the interrupt by interrupting the control flow of the processor. During the service
of this interrupt, external interrupts of equal or lower priority than vector 80 are
masked. When EOI is issued by software, the processor will remove the in-service
indication for external interrupt vector 80. External interrupt masking will then revert
back to the next highest priority in-service external interrupt, vector 45. External
interrupt vectors of equal or lower priority than vector 45 would remain masked until
EOI is issued by software. The in-service indication for vector 45 is then removed by
the write to EOI.
5.8.2.1 Re-enabling External Interrupt Delivery
When emerging from code in which external interrupt delivery is disabled and
interruption state collection is turned off, the following minimal code sequence
describes the architectural method with which to re-enable interruption collection and
enable external interrupts:
ssm PSR.ic
;;
srlz.d
ssm PSR.i
The processor does not ensure that enabling external interrupts is immediately
observed after the ssm PSR.i instruction. Software must perform a data serialization
operation after ssm PSR.i to ensure that external interrupt delivery is enabled prior to a
given point in program execution.
5.8.2.2 External Interrupt Sampling
Assuming that external interrupt delivery is currently disabled (PSR.i is 0), the following
minimal code sequence describes the architectural method with which to briefly open
the external interrupt window for external interrupt sampling (typically PSR.ic is 1 to
enable interruption collection):
2:120
// enable interruption collection
// guarantee that interruption collection is enabled
// enable external interrupts
Volume 2, Part 1: Interruptions