Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 838

input/output register specifiers.
3. From the ISR.code and FPSR trap enable controls, determine if a SWA Trap has
occurred, if not go to the last step.
4. Read the first IEEE rounded result from the FR output register.
5. From the opcode and the status field, decode the result range and precision.
6. From the ISR.code's FPA, O, U, and I status bits and the intermediate result,
produce the Itanium architecture specified result.
7. Place the result in the output FR register.
8. Update the flags in the appropriate status field of the FPSR, if required.
9. Update the ISR.code if required. (This is required if the SWA trap has been
translated into an IEEE trap.)
10. Check to see if an IEEE trap needs to be raised. If so, then queue it to the IEEE
Filter, otherwise continue checking for lower priority traps that may need to be
raised and if required invoke their handler. When finished, continue execution at
the next instruction.
8.1.1.3 Approximation Instructions and Architecturally Mandated SWA Faults
The scalar approximation instructions, frcpa and frsqrta, can raise architecturally
mandated SWA Faults. This occurs when their input operands are such that they are
potentially prevented from generating the correct result by the usual software
algorithms that are employed for divide and square root. The reasons for this are that
these algorithms may suffer from underflow, overflow, or loss of precision, because the
inputs or result are at the extremes of their range. For these special cases, the SWA
Fault handler must use alternate algorithms to provide the correct quotient or square
root and place that result in the floating-point destination register. The predicate
destination register is also cleared to indicate the result is not an approximation that
needs to be improved via the iterative algorithm.
The parallel approximation instructions fprcpa and fprsqrta have situations similar to
the scalar approximation instruction's architecturally mandated SWA Faults. This occurs
when their input operands are such that they are potentially prevented from generating
the correct result by the usual software algorithms that are employed for divide and
square root. For these special cases, instead of generating a SWA Fault, the parallel
approximation instructions indicate that software must use alternate algorithms to
provide the correct reciprocal or square-root reciprocal by clearing the destination
predicate register. The cleared predicate is the indication to the parallel IEEE-754 divide
and square root software algorithms that alternative algorithms are required to produce
the correct IEEE-754 quotient or square root.
8.1.2 The IEEE Floating-point Exception Filter
The Itanium architecture supports the reporting of the five IEEE-754 standard
floating-point exceptions and the IA-32 Denormal Operand exception. In the Itanium
architecture the Denormal Operand exception is expanded to the Denormal/Unnormal
Operand exception. When referring to the IEEE-754 exceptions in the Itanium
architecture the Denormal/Unnormal Operand exception is included.
2:590 Volume 2, Part 2: Floating-point System Software