Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 738

PAL_VPS_RESUME_NORMAL
Table 11-122. Virtual Processor Settings in Architectural Resources for
External Interrupt Control
Registers
Data/Instruction Breakpoint
Registers
Performance Monitor
Configuration Registers
Performance Monitor Data
Registers
a. Interval Timer Offset register is not supported on all processor implementations. See
Timer Offset (ITO – CR4)" on page 2:34
Table 11-123. Processor Status Register Settings for Virtual Processor
Field
User Mask = PSR{5:0}
rv 0
be 1
up 2
ac 3
mfl 4
mfh 5
System Mask = PSR{23:0}
ic 13
i 14
pk 15
rv 12:6,
16
dt 17
dfl 18
dfh 19
sp 20
pp 21
di 22
si 23
PSR.l = PSR{31:0}
db 24
lp 25
tb 26
rt 27
rv 31:28
PSR{63:0}
2:490
PAL_VPS_RESUME_NORMAL and PAL_VPS_RESUME_HANDLER
Resource
The external interrupt control registers contain the state of the virtual
processor if d_extint in Virtualization Disable Control (vdc) is 1. Otherwise
the external interrupt control registers are virtualized by the VMM and
contain VMM state.
The data/instruction breakpoint registers contain the state of the virtual
processor if d_ibr_dbr in Virtualization Disable Control (vdc) is 1.
Otherwise the data/instruction breakpoint registers are virtualized by the
VMM and contain VMM state.
The performance monitor configuration registers contain the state of the
virtual processor if d_pmc in Virtualization Disable Control (vdc) is 1.
Otherwise the performance monitor configuration registers are virtualized
by the VMM and contain VMM state.
Contain the state of the virtual processor.
Execution
Bits
Reserved
Contain user mask of the virtual processor.
Must be 1.
VMM-specific.
Reserved
Must be 1.
VMM-specific.
VMM-specific.
Contains the lp bit of the virtual processor.
Contains the tb bit of the virtual processor.
Must be 1.
Reserved
Description
for details.
Description
Volume 2, Part 1: Processor Abstraction Layer
Section 3.3.4.4, "Interval