Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 354

Aborts, external interrupts, RSE or instruction-fetch-related faults that happen to occur
on a speculative load are always raised (since they are not related to the speculative
load instruction). Illegal Operation faults and Disabled Floating-point Register faults
that occur on a speculative load are always raised.
Processing of exception conditions for speculative and speculative advanced loads is
done in three stages: qualification, deferral and prioritization.
During the execution of a load instruction, multiple exception conditions may be
detected simultaneously. For non-speculative loads these exception conditions are
prioritized and only the highest priority one raises a fault. For speculative loads,
however, some exception conditions may be deferred. As a result, it is possible for
lower priority exceptions, which are not also deferred, to raise a fault. For some
exception conditions, though, other lower priority conditions are meaningless, and are
said to be qualified, or precluded. Exception qualification is described in
Table 5-3.
Exception Condition
Register NaT Consumption
(NaT'ed address)
Unimplemented Data Address
Alternate Data TLB
VHPT data
Data TLB
Data Page Not Present
Data NaT Page Consumption
Data Key Miss
Data Key Permission
Data Access Rights
Data Access Bit
Data Debug
Unaligned Data Reference
Unsupported Data Reference
After exception conditions are detected and qualified, the remaining exception
conditions are checked for deferral. Deferral occurs after fault qualification and
determines which memory access exceptions raised by speculative loads are
automatically deferred by hardware.
2:106
Exception Qualification
none
Register NaT Consumption
Register NaT Consumption
Register NaT Consumption
Register NaT Consumption
Register NaT Consumption
Unimplemented Data Address
VHPT data
Register NaT Consumption
Unimplemented Data Address
VHPT data
Register NaT Consumption
Unimplemented Data Address
VHPT data
Register NaT Consumption
Unimplemented Data Address
VHPT data
Data TLB
Register NaT Consumption
Unimplemented Data Address
VHPT data
Register NaT Consumption
Unimplemented Data Address
VHPT data
Register NaT Consumption
Register NaT Consumption
Register NaT Consumption
Unimplemented Data Address
VHPT data
Precluded by Concurrent Exception Condition
Unimplemented Data Address
Unimplemented Data Address
Unimplemented Data Address
Data TLB
Alternate Data TLB
Data TLB
Alternate Data TLB
Data Page Not Present
Data TLB
Alternate Data TLB
Data Page Not Present
Alternate Data TLB
Data Page Not Present
Data Key Miss
Data TLB
Alternate Data TLB
Data Page Not Present
Data TLB
Alternate Data TLB
Data Page Not Present
Unimplemented Data Address
Unimplemented Data Address
Data TLB
Alternate Data TLB
Data Page Not Present
Table 5-3.
Volume 2, Part 1: Interruptions