Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 404

Processor implementations may not populate the entire PMC/PMD register space.
Reading of an unimplemented PMC or PMD register returns zero. Writes to
unimplemented PMC or PMD registers are ignored; i.e., the written value is discarded.
Writes to PMD and PMC and reads from PMC are privileged operations. At non-zero
privilege levels, these operations result in a Privileged Operation fault, regardless of the
register address.
Reading of PMD registers by non-zero privilege level code is controlled by PSR.sp. When
PSR.sp is one, PMD register reads by non-zero privilege level code return zero.
Figure 7-3.
Performance Counter
Overflow Status Registers
pmc
0
pmc
1
pmc
2
pmc
3
pmc
pmc
pmc
Implementation-dependent Performance Monitoring Register Set
7.2.1 Generic Performance Counter Registers
Generic performance counter registers are PMC/PMD pairs that contiguously populate
the PMC/PMD name space starting at index 4. At least 4 performance counter register
pairs (PMC/PMD[4]..PMC/PMD[7]) are implemented in all processor models. Each
counter can be configured to monitor events for any combination of privilege levels and
one of several event metrics. The number of performance counters is implementation
specific. The figures and tables use the symbol "p" to represent the index of the last
implemented generic PMC/PMD pair. The bit-width W of the counters is also
implementation specific.
2:156
Performance Monitor Register Set
Generic Performance Monitoring Register Set
63 0
Performance Counter
Configuration Registers
63 0
4
5
p
63 0
pmc
pmd
0
pmd
pmc
1
pmd
2
pmd
3
pmc
Performance Counter
Data Registers
63 0
pmd
4
pmd
5
pmd
p
63 0
pmd
p+1
pmd
p+2
pmd
255
Volume 2, Part 1: Debugging and Performance Monitoring
Processor Status Register
63 0
PSR
Default Control Register
63 0
cr
DCR
0
Performance Monitor
Vector Register
63 0
cr
PMV
73
63 0
p+1
p+2
255