Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 355

Deferral is controlled by PSR.ed, PSR.it, PSR.ic, the speculative deferral control bits in
the DCR, the exception deferral bit of the code page's instruction TLB entry (ITLB.ed),
and the memory attribute of the referenced data page. The speculative load and
speculative advanced load exception deferral conditions are as follows:
• When PSR.ic is 0 and regardless of the state of DCR, and ITLB.ed bits (see
Table
• Regardless of the state of DCR, PSR.it, PSR.ic, and ITLB.ed bits, Unimplemented
Data Address exception conditions and Data NaT Page Consumption exception
conditions (caused by references to NaTPages) are always deferred.
• When PSR.it and ITLB.ed are both 1, and the appropriate DCR bit is 1 for the
exception, the speculative load exception is deferred.
• When PSR.it and ITLB.ed are both 1, Unaligned Data Reference exception
conditions are deferred.
The conditions for deferral are given in
(DCR – CR0)" on page
Table 5-4.
Register NaT Consumption (NaT'ed address)
Unimplemented Data Address
Alternate Data TLB
VHPT data
Data TLB
Data Page Not Present
Data NaT Page Consumption
Data Key Miss
Data Key Permission
Data Access Rights
Data Access Bit
Data Debug
Unaligned Data Reference
Unsupported Data Reference
The conditions for spontaneous deferral are given in
PAL_PROC_GET_FEATURES – Get Processor Dependent Features (17) procedure for
details on enabling/disabling spontaneous deferral.
Table 5-5.
(PSR.ic && PSR.it && ITLB.ed && spontaneous_deferral_enabled())
After checking for deferral, execution of a speculative load instruction proceeds as
follows:
• When PSR.ed is 1, then a deferred exception indicator (NaT bit or NaTVal) is written
to the load target register, regardless of whether it has an exception or not and
regardless of the state of DCR, PSR.it, PSR.ic and the ITLB.ed bits.
• If PSR.ed is 0 and there is at least one exception condition which is neither
precluded nor deferred, then a fault is taken corresponding to the highest-priority
Volume 2, Part 1: Interruptions
5-2), all exception conditions related to the data reference are deferred.
2:31.
Qualified Exception Deferral
Qualified Exception
Spontaneous Deferral
Implementation-dependent condition may optionally be deferred if
Table 5-4. See also "Default Control Register
Deferred If
always
always
!PSR.ic || (PSR.it && ITLB.ed && DCR.dm)
!PSR.ic || (PSR.it && ITLB.ed && DCR.dm)
!PSR.ic || (PSR.it && ITLB.ed && DCR.dm)
!PSR.ic || (PSR.it && ITLB.ed && DCR.dp)
always
!PSR.ic || (PSR.it && ITLB.ed && DCR.dk)
!PSR.ic || (PSR.it && ITLB.ed && DCR.dx)
!PSR.ic || (PSR.it && ITLB.ed && DCR.dr)
!PSR.ic || (PSR.it && ITLB.ed && DCR.da)
!PSR.ic || (PSR.it && ITLB.ed && DCR.dd)
!PSR.ic || (PSR.it && ITLB.ed)
always
Table 5-5. See the
2:107