Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 559

to register its PALE_PMI entrypoint, processor operation is undefined. If a SAL related
PMI is seen before the SAL PMI handler is registered, the PAL PMI code will just return
to the interrupted context
Figure 11-7.
The hardware events that can cause the PMI request are referred to as PMI events. PMI
events are asynchronous interrupts higher priority than all external interrupts and are
only maskable when the system software is processing very critical tasks with
PSR.ic=0. When PSR.ic is 1, PMI events are unmasked. PSR.i has no effect on PMI
events. All PMI events are internally latched into an array of implementation-specific
latches in the processor. The PAL PMI handler reads the latches to determine what PMI
vector requests are pending and dispatches them in priority order.
PMI events and their priority.
Table 11-14. PMI Events and Priorities
a. PMI pin is not required to be present on all systems.
PMI messages can be delivered by an external interrupt controller, or as an
inter-processor interrupt using delivery mode 010.
vector assignments. Vectors 4-15 are reserved for PAL, and within these PAL vectors, a
higher vector number has higher priority. Vectors 1-3 are available for SAL to use, and
within these SAL vectors, a higher vector number has higher priority. A PMI pin event,
when the PMI pin
to the SAL PMI handler in GR 24.
Table 11-15. PMI Message Vector Assignments
Priority
Low
High
1. PMI pin is not required to be present. Software can query the presence of PMI pin via the
PAL_PROC_GET_FEATURES procedure call.
Volume 2, Part 1: Processor Abstraction Layer
PMI Entrypoints
PAL
PALE_PMI
PMI Events
PMI message for PAL (vectors 4-15)
PMI message for SAL (vectors 1-3)
a
PMI pin (vector 0)
1
is present, is indicated by vector 0. The PMI vector number is passed
Vector
0 PMI pin
1
2 Available for SAL firmware
3
SAL
SALE_PMI
Table 11-15
Description
OS
Table 11-14 lists the
Priority
High
Low
shows the PMI message
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