Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 610

Table 11-58. System Register Conventions (Continued)
Name
CMCV
LRR0-LRR1
RR
PKR
TR
TC
IBR/DBR
PMC
PMD
a. On some implementations, PAL virtualization support procedures may program IVA to a different value. Refer
to the description of the PAL virtualization procedures for details.
b. If an implementation provides a means to read TRs for PAL, this should be preserved.
c. The PAL_MC_ERROR_INJECT may modify these registers if the caller is using the triggering capability.
Refer to
d. No PAL procedure writes to the PMD. Depending on the PMC, the PMD may be kept counting performance
monitor events during a procedure call. The exception is PAL_TEST_PROC, which tests the performance
counters.
11.10.2.2.3 General Registers
PAL will use one of two general register calling conventions described in
Section 11.10.2.1, "Overview of Calling Conventions" on page
availability of memory and the stacked registers at the time of the call. The following
tables describe the contents of the general registers.
Table 11-59. General Registers – Static Calling Convention
Register
GR0
GR1
GR2 - GR3
GR4 - GR7
GR8 - GR11
GR12
GR13
GR14 - GR27
GR28 - GR31
Bank 0 Registers
(GR16 - GR23)
Bank 0 Registers
(GR 24 - GR31)
GR32 - GR127
Table 11-60. General Registers – Stacked Calling Conventions
Register
GR0
GR1
GR2 - GR3
GR4 - GR7
2:362
Corrected Machine Check Vector
Local Redirection Registers 0-1
Region Registers
Protection Key Registers
Translation Registers
Translation Cache
Break Point Registers
Performance Monitor Control Registers
Performance Monitor Data Registers
"PAL_MC_ERROR_INJECT – Inject Processor Error (276)" on page 2:421
always 0
preserved
scratch, used with 22 bit immediate add
preserved
scratch, procedure return value
preserved
unchanged
scratch
input arguments, scratch (PAL index must be passed in GR28)
preserved
scratch
unchanged
always 0
preserved
scratch, used with 22 bit immediate add
preserved
Description
Conventions
Conventions
Volume 2, Part 1: Processor Abstraction Layer
Class
unchanged
unchanged
preserved
preserved
b
unchanged
scratch
c
preserved
preserved
d
unchanged
for more information.
2:358, depending on the